+ endif
+
+ " The default highlighting.
+ HiLink verilogCharacter Character
+ HiLink verilogConditional Conditional
+ HiLink verilogRepeat Repeat
+ HiLink verilogString String
+ HiLink verilogTodo Todo
+ HiLink verilogComment Comment
+ HiLink verilogConstant Constant
+ HiLink verilogLabel Tag
+ HiLink verilogNumber Number
+ HiLink verilogOperator Special
+ HiLink verilogPrototype Statement
+ HiLink verilogStatement Statement
+ HiLink verilogGlobal Define
+ HiLink verilogDirective SpecialComment
+ HiLink verilogEscape Special
+ HiLink verilogMethod Function
+ HiLink verilogTypeDef TypeDef
+ HiLink verilogObject Type
+
+ delcommand HiLink
+endif
+
+let b:current_syntax = "verilog_systemverilog"
+
+" Restore cpoptions
+let &cpoptions=oldcpo
+
+" vim: sts=4 sw=4
diff --git a/bundle/verilog/test/errorformat.txt b/bundle/verilog/test/errorformat.txt
new file mode 100644
index 000000000..7b93e3696
--- /dev/null
+++ b/bundle/verilog/test/errorformat.txt
@@ -0,0 +1,38 @@
+### iverilog E=5, W=0
+path/file.v:5: syntax error
+path/file.v:5: error: Invalid module instantiation
+path/file.v:18: syntax error
+path/file.v:15: error: Syntax error in instance port expression(s).
+path/file.v:47: error: Invalid module instantiation
+
+### verilator E=2, W=3
+%Warning-ASSIGNDLY: test.v:1: Unsupported: Ignoring delay on this assignment/primitive.
+%Warning-DECLFILENAME: test.v:2: Filename 'test' does not match MODULE name: something
+%Warning-IMPLICIT: test.v:3: Signal definition not found, creating implicitly: something
+%Error: test.v:4: Pin not found: something
+%Error: test.v:3:9: syntax error, unexpected or, expecting ',' or ';'
+
+### ncverilog E=6, W=1
+ rcounter <= 10'b11111111111;
+ |
+ncvlog: *W,INTOVF (test.v,17|34): bit overflow during conversion from text [2.5(IEEE)] (10 bits).
+ assignn out = rcounter;
+ |
+ncvlog: *E,EXPLPA (test.v,23|14): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
+ncsim: *E,ASRTST (filename.sv,769): (time 0 FS) Assertion assertionname has failed
+ncsim: *E,TRNULLID: NULL pointer dereference.
+File: filename.sv, line = 62, pos = 36
+ncsim: *E,ASRTST (filename.sv,769): (time 0 FS) Assertion assertion_name has failed
+ncsim: *E,SOMECADENCEERRORCODE: Message
+ncsim: *E,ASRTST (filename.sv,123|12): Reason
+ncsim: irun 11.11-s111: Started on May 11, 1111 at 11:11:11 IST
+
+### spyglass E=1, W=1
+STX_VE_481 Syntax path/file.v 1 Syntax error near ( } )
+[66] UndrivenNUnloaded-ML WARNING Warning path/file.v 1 2 UndrivenNUnloaded-ML : Detected undriven and unloaded(unconnected) net
+
+### UVM E=2, W=1, L=1
+UVM_FATAL /path/file.sv(5) @ 1000: text
+UVM_ERROR /path/file.sv(5) @ 1000: text
+UVM_WARNING /path/file.sv(5) @ 1000: text
+UVM_INFO /path/file.sv(5) @ 1000: text
diff --git a/bundle/verilog/test/folding.v b/bundle/verilog/test/folding.v
new file mode 100644
index 000000000..c24c0dda7
--- /dev/null
+++ b/bundle/verilog/test/folding.v
@@ -0,0 +1,294 @@
+// all
+// | all,block_nested
+// | | all,block_named
+
+function f; //<1><1><1>
+begin //<2><2><1>
+ //<2><2><1>
+end //<2><2><1>
+endfunction : f //<1><1><1>
+
+task t; //<1><1><1>
+ //<1><1><1>
+begin //<2><2><1>
+ state = something(); //<2><2><1>
+ begin : block1 //<3><3><2>
+ state = 2'b00; //<3><3><2>
+ if (a <= b) begin //<4><4><2>
+ begin : block2 //<5><5><3>
+ end // block2 //<5><5><3>
+ state = 2'b11; //<4><4><2>
+ begin //<5><5><2>
+ end //<5><5><2>
+ end //<4><4><2>
+ begin : block3 //<4><4><3>
+ end // block3 //<4><4><3>
+ begin //<4><4><2>
+ end //<4><4><2>
+ end // block1 //<3><3><2>
+end //<2><2><1>
+ //<1><1><1>
+endtask : t //<1><1><1>
+
+/* //<1><1><1>
+* //<1><1><1>
+* function in_comment; //<1><1><1>
+* //<1><1><1>
+* endfunction //<1><1><1>
+* //<1><1><1>
+*/ //<1><1><1>
+
+extern function e_func (x, y); //<0><0><0>
+extern static function es_func (x, y); //<0><0><0>
+extern protected function ep_func (x, y); //<0><0><0>
+extern local function el_func (x, y); //<0><0><0>
+
+ pure virtual function pv_func (x); //<0><0><0>
+ pure virtual static function pvs_func (x); //<0><0><0>
+ pure virtual protected function pvp_func (x); //<0><0><0>
+ pure virtual local function pvl_func (x); //<0><0><0>
+
+extern virtual function ev_func (x); //<0><0><0>
+extern virtual static function evs_func (x); //<0><0><0>
+extern virtual protected function evp_func (x); //<0><0><0>
+extern virtual local function evl_func (x); //<0><0><0>
+
+extern pure virtual function epv_func (x); //<0><0><0>
+extern pure virtual static function epvs_func (x); //<0><0><0>
+extern pure virtual protected function epvp_func (x); //<0><0><0>
+extern pure virtual local function epvl_func (x); //<0><0><0>
+
+extern task e_task (x, y); //<0><0><0>
+extern static task es_task (x, y); //<0><0><0>
+extern protected task ep_task (x, y); //<0><0><0>
+extern local task el_task (x, y); //<0><0><0>
+
+ pure virtual task pv_task (x); //<0><0><0>
+ pure virtual static task pvs_task (x); //<0><0><0>
+ pure virtual protected task pvp_task (x); //<0><0><0>
+ pure virtual local task pvl_task (x); //<0><0><0>
+
+extern virtual task ev_task (x, y); //<0><0><0>
+extern virtual static task evs_task (x, y); //<0><0><0>
+extern virtual protected task evp_task (x, y); //<0><0><0>
+extern virtual local task evl_task (x, y); //<0><0><0>
+
+extern pure virtual task epv_task (x, y); //<0><0><0>
+extern pure virtual static task epvs_task (x, y); //<0><0><0>
+extern pure virtual protected task epvp_task (x, y); //<0><0><0>
+extern pure virtual local task epvl_task (x, y); //<0><0><0>
+
+
+/** //<1><1><1>
+* Static function //<1><1><1>
+*/ //<1><1><1>
+static function f1; //<1><1><1>
+endfunction //<1><1><1>
+
+specify //<1><1><1>
+ //<1><1><1>
+endspecify //<1><1><1>
+
+covergroup cov; //<1><1><1>
+ //<1><1><1>
+endgroup //<1><1><1>
+
+property prop; //<1><1><1>
+endproperty //<1><1><1>
+
+sequence //<1><1><1>
+endsequence //<1><1><1>
+
+// Classes //<0><0><0>
+class class_a; //<1><1><1>
+ //<1><1><1>
+endclass : class_a //<1><1><1>
+
+class class_b; //<1><1><1>
+ class class_b1; //<2><2><2>
+ //<2><2><2>
+ endclass : class_b1 //<2><2><2>
+ //<1><1><1>
+ class class_b2; //<2><2><2>
+ //<2><2><2>
+ endclass : class_b2 //<2><2><2>
+endclass : class_b //<1><1><1>
+
+interface a; //<1><1><1>
+ //<1><1><1>
+ interface class b; //<2><2><2>
+ endclass : b //<2><2><2>
+ //<1><1><1>
+ clocking cb @ (posedge Clk); //<2><2><2>
+ endclocking : cb //<2><2><2>
+ //<1><1><1>
+endinterface : a //<1><1><1>
+
+typedef interface class my_itf_class; //<0><0><0>
+
+`ifdef A //<1><1><1>
+reg test; //<1><1><1>
+ //<1><1><1>
+// `ifdef A_1 //<1><1><1>
+// //<1><1><1>
+// `else //<1><1><1>
+// //<1><1><1>
+// `endif //<1><1><1>
+ //<1><1><1>
+`else //<1><1><1>
+ //<1><1><1>
+`endif //<1><1><1>
+
+`ifndef B //<1><1><1>
+ //<1><1><1>
+`elsif C //<1><1><1>
+ //<1><1><1>
+`elsif D //<1><1><1>
+ //<1><1><1>
+`else //<1><1><1>
+ //<1><1><1>
+`endif //<1><1><1>
+
+`ifdef E //<1><1><1>
+ //<1><1><1>
+ `ifndef E_1 //<2><2><2>
+ //<2><2><2>
+ `else //<2><2><2>
+ //<2><2><2>
+ `endif //<2><2><2>
+ //<1><1><1>
+ `ifndef E_2 //<2><2><2>
+ //<2><2><2>
+ `elsif E_3 //<2><2><2>
+ //<2><2><2>
+ `endif //<2><2><2>
+ //<1><1><1>
+`endif //<1><1><1>
+
+`ifdef A //<1><1><1>
+ //<1><1><1>
+ `ifdef B //<2><2><2>
+ //<2><2><2>
+ `else //<2><2><2>
+ //<2><2><2>
+ `endif //<2><2><2>
+ //<1><1><1>
+`elsif C //<1><1><1>
+ //<1><1><1>
+`else //<1><1><1>
+ //<1><1><1>
+`endif //<1><1><1>
+
+
+/* //<1><1><1>
+ `ifdef X //<1><1><1>
+ //<1><1><1>
+ `else //<1><1><1>
+ //<1><1><1>
+ `endif //<1><1><1>
+*/ //<1><1><1>
+
+ module_name #( //<1><1><1>
+ .PARAM1 (VALUE1) //<1><1><1>
+ ) //<1><1><1>
+ instance_name( //<1><1><1>
+ .port1 (net1), //<1><1><1>
+ .port2 (net2) //<1><1><1>
+ ); //<1><1><1>
+
+module_name instance_name( //<1><1><1>
+ .port1 (net1), //<1><1><1>
+ .port2 (net2) //<1><1><1>
+); //<1><1><1>
+
+module_name #(VALUE1) instance_name ( //<1><1><1>
+ .port1 (net1), //<1><1><1>
+ .port2 (net2) //<1><1><1>
+); //<1><1><1>
+
+module_name #(VALUE1) instance_name //<1><1><1>
+( //<1><1><1>
+ .port1 (net1), //<1><1><1>
+ .port2 (net2) //<1><1><1>
+); //<1><1><1>
+
+uvm_blocking_put_port #(trans) out; //<0><0><0>
+
+task t_multi_line( //<1><1><1>
+ input an_input //<1><1><1>
+); //<1><1><1>
+ //<1><1><1>
+endtask : t_multi_line //<1><1><1>
+
+ task t_multi_line_indented( //<1><1><1>
+ input an_input //<1><1><1>
+ ); //<1><1><1>
+ //<1><1><1>
+ endtask : t_multi_line //<1><1><1>
+
+if (cond1) begin //<1><1><0>
+ do1(); //<1><1><0>
+end else if (cond2) begin //<1><1><0>
+ do2(); //<1><1><0>
+ do3(); //<1><1><0>
+ do4(); //<1><1><0>
+end else begin //<1><1><0>
+ do5(); //<1><1><0>
+end //<1><1><0>
+
+if (cond1) //<0><0><0>
+ do1(); //<0><0><0>
+else if (cond2) begin //<1><1><0>
+ do2(); //<1><1><0>
+ begin //<2><2><0>
+ do2_1(); //<2><2><0>
+ end //<2><2><0>
+ do3(); //<1><1><0>
+ do4(); //<1><1><0>
+end else begin //<1><1><0>
+ do5(); //<1><1><0>
+end //<1><1><0>
+
+if (cond1) begin : b1 //<1><1><1>
+ do1(); //<1><1><1>
+end else if (cond2) begin : b2 //<1><1><1>
+ do2(); //<1><1><1>
+ do3(); //<1><1><1>
+ do4(); //<1><1><1>
+end else begin : b3 //<1><1><1>
+ do5(); //<1><1><1>
+end //<1><1><1>
+
+if (cond1) //<0><0><0>
+ do1(); //<0><0><0>
+else if (cond2) begin : b1 //<1><1><1>
+ do2(); //<1><1><1>
+ begin:b2 //<2><2><2>
+ do2_1(); //<2><2><2>
+ end //<2><2><2>
+ do3(); //<1><1><1>
+ do4(); //<1><1><1>
+end else begin //<1><1><1>
+ do5(); //<1><1><0>
+end else begin:b3 //<1><1><1>
+ do5(); //<1><1><1>
+end //<1><1><1>
+
+task something; //<1><1><1>
+fork //<1><1><1>
+ begin //<2><2><1>
+ begin //<3><3><1>
+ end //<3><3><1>
+ /* //<3><3><2>
+ begin //<3><3><2>
+ end //<3><3><2>
+ */ //<3><3><2>
+ end //<2><2><1>
+join //<1><1><1>
+endtask //<1><1><1>
+
+// spyglass disable_block SOMETHING //<1><1><1>
+assign a = b & c; //<1><1><1>
+// spyglass enable_block SOMETHING //<1><1><1>
+
+// vi: set expandtab softtabstop=4 shiftwidth=4:
diff --git a/bundle/verilog/test/folding.v.html b/bundle/verilog/test/folding.v.html
new file mode 100644
index 000000000..11da62d5c
--- /dev/null
+++ b/bundle/verilog/test/folding.v.html
@@ -0,0 +1,298 @@
+
+
+
+
+
+
+function f;
+begin
+
+end
+endfunction : f
+
+task t;
+
+begin
+ state = something();
+ begin : block1
+ state = 2'b00;
+ if (a <= b) begin
+ begin : block2
+ end
+ state = 2'b11;
+ begin
+ end
+ end
+ begin : block3
+ end
+ begin
+ end
+ end
+end
+
+endtask : t
+
+
+
+
+
+
+
+
+
+extern function e_func (x, y);
+extern static function es_func (x, y);
+extern protected function ep_func (x, y);
+extern local function el_func (x, y);
+
+ pure virtual function pv_func (x);
+ pure virtual static function pvs_func (x);
+ pure virtual protected function pvp_func (x);
+ pure virtual local function pvl_func (x);
+
+extern virtual function ev_func (x);
+extern virtual static function evs_func (x);
+extern virtual protected function evp_func (x);
+extern virtual local function evl_func (x);
+
+extern pure virtual function epv_func (x);
+extern pure virtual static function epvs_func (x);
+extern pure virtual protected function epvp_func (x);
+extern pure virtual local function epvl_func (x);
+
+extern task e_task (x, y);
+extern static task es_task (x, y);
+extern protected task ep_task (x, y);
+extern local task el_task (x, y);
+
+ pure virtual task pv_task (x);
+ pure virtual static task pvs_task (x);
+ pure virtual protected task pvp_task (x);
+ pure virtual local task pvl_task (x);
+
+extern virtual task ev_task (x, y);
+extern virtual static task evs_task (x, y);
+extern virtual protected task evp_task (x, y);
+extern virtual local task evl_task (x, y);
+
+extern pure virtual task epv_task (x, y);
+extern pure virtual static task epvs_task (x, y);
+extern pure virtual protected task epvp_task (x, y);
+extern pure virtual local task epvl_task (x, y);
+
+
+
+
+
+static function f1;
+endfunction
+
+specify
+
+endspecify
+
+covergroup cov;
+
+endgroup
+
+property prop;
+endproperty
+
+sequence
+endsequence
+
+
+class class_a;
+
+endclass : class_a
+
+class class_b;
+ class class_b1;
+
+ endclass : class_b1
+
+ class class_b2;
+
+ endclass : class_b2
+endclass : class_b
+
+interface a;
+
+ interface class b;
+ endclass : b
+
+ clocking cb @ (posedge Clk);
+ endclocking : cb
+
+endinterface : a
+
+typedef interface class my_itf_class;
+
+`ifdef A
+reg test;
+
+
+
+
+
+
+
+`else
+
+`endif
+
+`ifndef B
+
+`elsif C
+
+`elsif D
+
+`else
+
+`endif
+
+`ifdef E
+
+ `ifndef E_1
+
+ `else
+
+ `endif
+
+ `ifndef E_2
+
+ `elsif E_3
+
+ `endif
+
+`endif
+
+`ifdef A
+
+ `ifdef B
+
+ `else
+
+ `endif
+
+`elsif C
+
+`else
+
+`endif
+
+
+
+
+
+
+
+
+
+
+ module_name #(
+ .PARAM1 (VALUE1)
+ )
+ instance_name(
+ .port1 (net1),
+ .port2 (net2)
+ );
+
+module_name instance_name(
+ .port1 (net1),
+ .port2 (net2)
+);
+
+module_name #(VALUE1) instance_name (
+ .port1 (net1),
+ .port2 (net2)
+);
+
+module_name #(VALUE1) instance_name
+(
+ .port1 (net1),
+ .port2 (net2)
+);
+
+uvm_blocking_put_port #(trans) out;
+
+task t_multi_line(
+ input an_input
+);
+
+endtask : t_multi_line
+
+ task t_multi_line_indented(
+ input an_input
+ );
+
+ endtask : t_multi_line
+
+if (cond1) begin
+ do1();
+end else if (cond2) begin
+ do2();
+ do3();
+ do4();
+end else begin
+ do5();
+end
+
+if (cond1)
+ do1();
+else if (cond2) begin
+ do2();
+ begin
+ do2_1();
+ end
+ do3();
+ do4();
+end else begin
+ do5();
+end
+
+if (cond1) begin : b1
+ do1();
+end else if (cond2) begin : b2
+ do2();
+ do3();
+ do4();
+end else begin : b3
+ do5();
+end
+
+if (cond1)
+ do1();
+else if (cond2) begin : b1
+ do2();
+ begin:b2
+ do2_1();
+ end
+ do3();
+ do4();
+end else begin
+ do5();
+end else begin:b3
+ do5();
+end
+
+task something;
+fork
+ begin
+ begin
+ end
+
+
+
+
+ end
+join
+endtask
+
+
+assign a = b & c;
+
+
+
+
+
diff --git a/bundle/verilog/test/functions.vim b/bundle/verilog/test/functions.vim
new file mode 100644
index 000000000..eba5783d5
--- /dev/null
+++ b/bundle/verilog/test/functions.vim
@@ -0,0 +1,234 @@
+function! TestFold(...)
+ let fail = 0
+ let linenr = 4 "Start after header
+ if exists("a:1")
+ let index = a:1
+ else
+ let index = 0
+ endif
+ while linenr < line("$")
+ let line = getline(linenr)
+ let levels = substitute(line, '.\{-}<\(\d*\)>', '\1::', 'g')
+ let levels_list = split(levels, '::')
+ if len(line) == 0
+ " Empty lines can be used as separators and will have zero " folding
+ let level_expected=0
+ elseif index < 0 || (index >= len(levels_list))
+ " Abort if requested index is NOT available in the levels list
+ echo 'Invalid line format: (' . linenr . ')'
+ echo line
+ return 1
+ else
+ " Store expected indent level
+ let level_expected=levels_list[index]
+ endif
+ " Check indent level
+ let level = foldlevel(linenr)
+ if (level != level_expected)
+ let fail = 1
+ echo "Error: level=" . level . " level_expected=" . level_expected . " (" . linenr . ") >>>>" . line
+ endif
+ let linenr += 1
+ endwhile
+
+ if (fail == 1)
+ echo 'Fold test failed:'
+ echo 'g:verilog_syntax_fold_lst: ' . g:verilog_syntax_fold_lst
+ return 1
+ else
+ echo 'Fold test passed'
+ return 0
+ endif
+
+endfunction
+
+function! TestIndent()
+ let fail = 0
+ let fail_lines = ''
+ let linenr = 0
+ while linenr < line("$")
+ let linenr += 1
+ let line = getline(linenr)
+ let ind1 = indent(linenr)
+ execute 'normal! '.linenr.'gg=='
+ let ind2 = indent(linenr)
+ if ind1 != ind2
+ let fail = 1
+ if (fail_lines == '')
+ let fail_lines = linenr
+ else
+ let fail_lines = fail_lines.','.linenr
+ endif
+ endif
+ endwhile
+
+ if (fail == 1)
+ echo 'Indent test failed:'
+ echo fail_lines
+ return 1
+ else
+ echo 'Indent test passed'
+ return 0
+ endif
+
+endfunction
+
+function! TestEfm(tool, mode, search_uvm)
+ let expected_errors = 0
+ let expected_warnings = 0
+ let expected_lints = 0
+ let uvm_expected_errors = 0
+ let uvm_expected_warnings = 0
+ let uvm_expected_lints = 0
+
+ " Re-read test file
+ silent view test/errorformat.txt
+
+ " Obtain tool configuration from file
+ let config_found = 0
+ let linenr = 0
+ while linenr < line("$")
+ let linenr += 1
+ let line = getline(linenr)
+ " Tool config line
+ let tool_config = matchlist(line, '^### *' . tolower(a:tool) . ' E=\(\d\+\), *W=\(\d\+\)\(, *L=\(\d\+\)\)\?')
+ if len(tool_config) != 0
+ let expected_errors = tool_config[1]
+ if a:mode == 1
+ let expected_warnings = tool_config[2]
+ else
+ let expected_warnings = 0
+ endif
+ if a:mode <= 2
+ let expected_lints = tool_config[4]
+ else
+ let expected_lints = 0
+ endif
+ let config_found = 1
+ if !a:search_uvm
+ break
+ endif
+ endif
+ " UVM config line
+ let uvm_config = matchlist(line, '^### *UVM E=\(\d\+\), *W=\(\d\+\)\(, *L=\(\d\+\)\)\?')
+ if len(uvm_config) != 0
+ let uvm_expected_errors = uvm_config[1]
+ if len(uvm_config) > 1
+ let uvm_expected_warnings = uvm_config[2]
+ endif
+ if len(uvm_config) > 3
+ let uvm_expected_lints = uvm_config[4]
+ endif
+ let uvm_config_found = 1
+ if config_found
+ break
+ endif
+ endif
+ endwhile
+
+ if !config_found
+ echo 'Test for tool ' . tolower(a:tool) . ' was not found'
+ return 1
+ endif
+
+ " Calculate total expected errors
+ if a:search_uvm
+ let expected_errors += uvm_expected_errors
+ let expected_warnings += uvm_expected_warnings
+ let expected_lints += uvm_expected_lints
+ endif
+
+ " Setup 'errorformat' and 'makeprg'
+ call verilog_systemverilog#VerilogErrorFormat(a:tool, a:mode)
+ setlocal makeprg=cat\ %
+
+ " Populate quickfix window
+ silent! make!
+ redraw
+
+ " Check results
+ let errors = 0
+ let warnings = 0
+ let lints = 0
+ let qf_list = getqflist()
+ for qf_entry in qf_list
+ " Only check valid entries
+ if qf_entry.valid != 0
+ " Consider Fatal and matches without type as errors
+ if qf_entry.type == 'E' ||
+ \ qf_entry.type == 'F' ||
+ \ qf_entry.type == ''
+ let errors += 1
+ endif
+ if qf_entry.type == 'W'
+ let warnings += 1
+ endif
+ " Consider Info as lint
+ if qf_entry.type == 'L' ||
+ \ qf_entry.type == 'I'
+ let lints += 1
+ endif
+ endif
+ endfor
+ echo 'Results:'
+ echo ' Expected errors = ' . expected_errors . ', errors found = ' . errors
+ echo ' Expected warnings = ' . expected_warnings . ', warnings found = ' . warnings
+ echo ' Expected lints = ' . expected_lints . ', lints found = ' . lints
+ echo ' errorformat = ' . &errorformat
+ echo 'Quickfix contents:'
+ for qf_entry in qf_list
+ echo qf_entry
+ endfor
+ if errors == expected_errors && warnings == expected_warnings && lints == expected_lints
+ echo 'Error format test passed'
+ return 0
+ else
+ echo 'Error format test failed:'
+ return 1
+ endif
+endfunction
+
+function! TestSyntax(file_name, test_name)
+ let test_name=substitute(a:test_name, ',', '_', '')
+ if test_name == ""
+ let test_name="default"
+ endif
+ let ref_file_name='test/' . a:file_name . '.html'
+ let new_file_name='test/' . a:file_name . '.' . test_name . '.html'
+
+ execute 'silent view test/' . a:file_name
+ syntax enable
+
+ " Generate HTML version of the file
+ let g:html_line_ids=0
+ let g:html_number_lines=0
+ let g:html_no_progress=1
+ TOhtml
+ " Clean up resulting HTML to minimize differences with other
+ " versions of TOhtml script
+ 1,//-1 delete
+ /<\/body>/+1,$ delete
+ %s/ id='vimCodeElement'//e
+ " Write final buffer
+ execute 'w! ' . new_file_name
+ bd!
+
+ " Compare with reference
+ silent let output = system('diff ' . ref_file_name . ' ' . new_file_name)
+
+ if output == ""
+ echo 'Syntax test "' . a:file_name . '" with folding ' . test_name . ' passed'
+ echo ''
+ return 0
+ else
+ echo '=====DIFF START====='
+ echo output
+ echo '=====DIFF END======='
+ echo 'Syntax test "' . a:file_name . '" with folding ' . test_name . ' failed'
+ echo ''
+ return 1
+ endif
+
+endfunction
+
+" vi: set expandtab softtabstop=4 shiftwidth=4:
diff --git a/bundle/verilog/test/indent.sv b/bundle/verilog/test/indent.sv
new file mode 100644
index 000000000..5b7c27d16
--- /dev/null
+++ b/bundle/verilog/test/indent.sv
@@ -0,0 +1,1077 @@
+typedef class a;
+
+// Code based on: https://github.com/vhda/verilog_systemverilog.vim/issues/2
+class z;
+
+ // this is a comment
+ // -----------------
+ typedef struct {
+ real a;
+ int b;
+ int c;
+ real d; } ts;
+
+ ts s[];
+
+ // if there are
+ // more comments
+ typedef struct {
+ real a;
+ int b;
+ int c;
+ real d;
+ } ts2;
+
+ ts2 t[];
+
+ int unsigned cnt=0;
+
+ function new();
+ super.new();
+ endfunction;
+
+ virtual interface my_itf itf;
+
+ // Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/4
+ task run_phase(uvm_phase phase);
+
+ assert(my_seq.randomize());
+ my_seq.start(low_sequencer_h);
+
+ assert(my_seq.randomize() with {Nr==6;});
+ my_seq.start(low_sequencer_h);
+
+ assert(my_seq.randomize() with
+ {Nr==6; Time==8;});
+ my_seq.start(low_sequencer_h);
+
+ assert(
+ my_seq.randomize() with
+ {Nr==6; Time==8;}
+ );
+ my_seq.start(low_sequencer_h);
+
+ // Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/5
+ fork
+ begin : isolating_thread
+ do_something();
+ end : isolating_thread
+ join
+ // End of copied code
+
+ // Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/15
+ assert(out>0) else $warning("xxx");
+ $display("Hi");
+
+ assert(out>0)
+ else $warning("xxx");
+ $display("Hi");
+
+ assert(out>0) else $warning("xxx");
+ $display("Hi");
+ $display("Hi");
+ // End of copied code
+
+ assert(out>0)
+ else
+ $warning("xxx");
+ $display("Hi");
+
+ if (1 > 0) $display("1 > 0");
+ else $display("1 < 0");
+ $display();
+
+ endtask
+ // End of copied code
+
+ // Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/7
+ task run_phase2(uvm_phase phase);
+ assert(out>0) else $warning("xxx");
+ assert(out>0) else $warning("xxx");
+ foreach(out[i]) begin
+ out[i]=new;
+ end
+ endtask
+ // End of copied code
+
+ /*
+ *
+ *
+ *
+ */
+
+ // Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/12
+ task my_seq::body();
+ `uvm_info({get_type_name(),"::body"}, "something" ,UVM_HIGH)
+ req = my_seq_item_REQ::type_id::create("req");
+ endtask
+ // End of copied code
+
+ // Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/14
+ pure virtual function void a(input int unsigned N, ref t Data);
+ pure virtual function void b(input int unsigned N, ref t Data);
+ pure virtual function void c(input int unsigned N, ref t Data);
+ // End of copied code
+
+ // Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/17
+ function void sink_driver::build_phase(uvm_phase phase);
+ if (!uvm_config_db #(sink_agent_config)::get(this, "", "sink_agent_config", m_cfg) )
+ `uvm_fatal("CONFIG_LOAD", "Cannot get() configuration sink_agent_config from uvm_config_db. Have you set() it?")
+ // OK to do this herE>
+ foreach(rand_bool_gen[ch]) begin
+ rand_bool_gen[ch]=new();
+ end
+ endfunction
+ // End of copied code
+
+ // Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/41
+ `uvm_info("TAG", "message", UVM_MEDIUM)
+
+ if (condition)
+ `uvm_info("TAG", "message1", UVM_MEDIUM)
+ else
+ `uvm_info("TAG", "message2", UVM_NONE)
+ // End of copied code
+
+ // Other tests
+ task fork_test;
+ fork
+ do_something1();
+ do_something2();
+ join_none // {}
+ do_something3();
+ endtask
+
+ task while_one_line;
+ while (1)
+ do_something();
+
+ (* full_case=1 *)
+ (* parallel_case=1 *)
+ case (a)
+ endcase
+
+ (* full_case,
+ parallel_case=1 *)
+ case (a)
+ endcase
+
+ endtask
+
+ function less_or_equal;
+ if (a <= b)
+ less_or_equal = a;
+ endfunction
+
+ task while_block;
+ while (1)
+ begin
+ do_something();
+ end
+ endtask
+
+ task while_block2;
+ while (1) begin
+ do_something();
+ end
+ endtask
+
+ virtual task virtual_task;
+ while (1) begin
+ do_something();
+ end
+ endtask
+
+ virtual function virtual_function;
+ while (1) begin
+ do_something();
+ end
+
+ do
+ do_something();
+ while (1);
+
+ do begin
+ do_something();
+ end while (1);
+
+ endfunction
+
+ //function old_style_function_with_var(
+ // input a
+ //);
+ //reg test;
+ //begin
+ // do_something1();
+ // do_something2();
+ // begin
+ // do_something3();
+ // end
+ //end
+ //endfunction
+
+ //function old_style_function_without_var(
+ // input a
+ //);
+ //begin
+ // do_something1();
+ // do_something2();
+ // begin
+ // do_something3();
+ // end
+ //end
+ //endfunction
+
+ //function old_style_function_one_line_with_var(input a);
+ // reg x;
+ //begin
+ // do_something1();
+ // do_something2();
+ // begin
+ // do_something3();
+ // end
+ //end
+ //endfunction
+
+ //function old_style_function_one_line_without_var(input a);
+ //begin
+ // do_something1();
+ // do_something2();
+ // begin
+ // do_something3();
+ // end
+ //end
+ //endfunction
+
+ function void hello();
+ foreach (element[i])
+ if (hi)
+ if (hi) /* comment */ begin /* comment */
+ if (hi) begin
+ foreach (element[i])
+ if (condition0)
+ if (condition1) begin
+ var0 <= 0;
+ end
+ else begin
+ if (1) begin
+ var1 <= 1;
+ something();
+ if (1)
+ if (1) begin
+ something();
+ end
+ else
+ if (1)
+ if (1) begin
+ if (1)
+ something();
+ else begin
+ something();
+ end
+ end
+ else if (1)
+ something();
+ else
+ something();
+
+ if (1)
+ something();
+
+ if (1) begin
+ something();
+ end else
+ something();
+
+ if (1) begin
+ something();
+ end else
+ something();
+
+ if (1)
+ // Nested case
+ case(value)
+ 0,
+ 1:
+ case(value) inside
+ [0:20]:;
+ 21: something();
+ 22:;
+ default: something();
+ endcase
+ 2:;
+ 3:;
+ endcase
+
+ if (1)
+ something();
+
+ /* end */
+
+ something();
+ /* end */
+ something();
+ end
+ end
+ deindent_x2_please();
+ /* end */
+ dont_deindent_please();
+ end
+ deindent_please();
+ end
+ deindent_please();
+ dont_deindent_please();
+ endfunction : hello
+
+ function void hello();
+ if (1)
+ fork
+ something();
+ something();
+ begin
+ something();
+ end
+ begin
+ fork
+ if (1) // begin
+ if (1)
+ if (1) begin // comment
+ something();
+ if (1) begin
+ end
+ something();
+ end
+ something();
+ join
+ if (1)
+ do
+ something();
+ while(1);
+ else
+ do
+ something();
+ while (1) ;
+ something();
+ end
+ if (1)
+ foreach (objects[i])
+ if (1)
+ if (1) begin
+ something();
+ fork begin
+ something();
+ end join
+ end
+ something();
+ join_none
+
+ // Code from: // https://github.com/vhda/verilog_systemverilog.vim/issues/158
+ fork
+ p1: begin
+ myvar=1'b1;
+ `info("some message with the word join");
+ end
+ p2: begin
+ myvar2=1'b1;
+ end
+ join
+ // End of copied code
+ endfunction : hello
+
+ local static function void hello();
+ const bit variable1 =
+ func_call(object_t) && structue_t.field_t.source != ENUM_VALUE &&
+ object_t.field_t && variable0;
+
+ const bit variable1 =
+ func_call(object_t) && structue_t.field_t.source != ENUM_VALUE
+ && object_t.field_t && variable0;
+
+ const bit variable2 =
+ object_t.field_t && object_t.field_t.source == ENUM_VALUE;
+
+ bit variable3;
+
+ // Multi-line if with no begin
+ if (variable && variable && variable &&
+ variable)
+ indent();
+
+ de_indent();
+
+ // Multi-line if with begin with a line starting with &&
+ if (variable && variable && variable
+ && variable
+ && variable) begin
+ indent();
+ stay();
+ end
+
+ de_indent();
+
+ variable = variable
+ || variable || variable;
+
+ variable = variable ||
+ variable || variable;
+
+ variable = (variable == CONSTANT) &
+ variable &
+ variable;
+
+ wire var0 = a &
+ b;
+
+ wire [1:0] var1 = a &
+ b;
+
+ var2[0] = a &
+ b;
+
+ {var0, var1} = a &
+ b;
+
+ some_struct.field1 = a &
+ b;
+
+ some_type #(params) some_object = cond0 ? a :
+ cond1 ? b : c;
+
+ if (1) begin
+ if (1
+ && 1)
+ something();
+ end
+
+ endfunction
+
+endclass
+
+class a;
+ class nested;
+ import "DPI-C" function void c_print();
+ int b;
+ endclass
+endclass
+
+clocking ck1 @(posedge clk);
+ default input #1step output negedge;
+ input a;
+ output y;
+endclocking
+
+// TODO: Unsupported
+// class a;
+// typedef class a;
+// endclass
+
+// Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/14
+virtual class base;
+
+ extern function void x(input int unsigned N, ref t Data);
+ extern function void y(input int unsigned N, ref t Data);
+
+ pure virtual function void a(input int unsigned N, ref t Data);
+ pure virtual function void b(input int unsigned N, ref t Data);
+ pure virtual function void c(input int unsigned N, ref t Data);
+
+endclass;
+// End of copied code
+
+// Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/49
+module MyModule #(
+ parameter A = 1,
+ parameter B = 2
+)(
+ input I,
+ output O
+);
+
+
+wire Val_IP = !In_Pkt_S_Bus_enf ||
+ ((Pls_Don || ResVal) && (Pls_Res || ResFnd));
+
+wire Val_IP =
+ !In_Pkt_S_Bus_enf || // A, B, C
+ ((Pls_Don || ResVal) && (Pls_Res || ResFnd));
+
+wire Val_IP = !In_Pkt_S_Bus_enf ?
+ ((Pls_Don || ResVal) && (Pls_Res == ResFnd)) :
+ ((Pls_Don || ResVal) && (Pls_Res || ResFnd));
+
+MyModule #(
+ .A (1),
+ .B (2)
+) Module_1 (
+ .I (wire1),
+ .O (wire2)
+);
+
+or or_0();
+
+endmodule
+// End of copied code
+
+// Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/51
+case (Signal)
+ 2'd0: begin Result <= 0; end
+ 2'd1: begin Result <= 1; end
+ 2'd2: begin Result <= 2; end
+ default: begin Result <= 0; end
+endcase
+// End of copied code
+
+interface class base;
+
+ pure virtual function void a(input int unsigned N, ref t Data);
+ pure virtual function void b(input int unsigned N, ref t Data);
+ pure virtual function void c(input int unsigned N, ref t Data);
+
+endclass;
+
+module m #(1)
+(
+ portA,
+ portB
+);
+
+// Nested modules (IEEE - 1800-2012, section 23.4)
+module a;
+endmodule
+
+endmodule
+
+module m (
+ portA,
+ portB
+);
+
+device d0 (
+ .port (port[1]),
+ .port2(), // comment
+ .portA(port[2])
+);
+
+// Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/6
+device d1 (
+ .port (port[1]),
+ // .port2(), // comment
+ .*
+);
+
+`ifdef DO_THIS
+ device d1 (
+ .port (port[1]),
+ /* comment line 1
+ * comment line2 */
+ .port2(),
+ .*
+ );
+`endif
+
+`ifdef DO_THIS
+ device2 d2 (
+ .out,
+ .a,
+ .b(B)/*,
+ TODO .c(C) port not implemented yet */
+ );
+`endif
+// End of copied code
+
+device d1 (
+ .port (port[1]),
+ // .port1(), comment
+ /**/.port2(), // comment
+ /*.port3(), */
+ // .port4(), comment
+ .portA(port[2])
+);
+
+`define VALUE 3
+
+`define VALUE_MULTI_LINE \
+ 16'hFF
+
+`ifdef V95
+ device d2 ( out, portA, portB );
+ device d2 ( out, portA, portB );
+ `ifdef V95
+ device d2 ( out, portA, portB );
+ device d2 ( out, portA, portB );
+ `endif
+`elsif V2K
+ device d2 ( .out(out), .* );
+ device d2 ( out, portA, portB );
+ `ifndef SWAP
+ device d3 ( .out(out), .* );
+ device d2 ( .out(out), .* );
+ `else
+ device d3 ( .out(out), .portA(portB), .portB(portA) );
+ device d2 ( .out(out), .* );
+ `endif
+`endif
+`ifndef SWAP
+ device d3 ( .out(out), .* );
+ device d2 ( .out(out), .* );
+`else
+ device d3 ( .out(out), .portA(portB), .portB(portA) );
+ device d2 ( .out(out), .* );
+`endif
+
+endmodule
+
+class a;
+endclass : a
+
+module a import some_pkg::*;
+(
+ input clk,
+ output x
+);
+
+always @ (posedge clk)
+begin
+end
+
+always
+ x <= 1;
+
+always
+begin
+ x <= 1;
+ statement();
+end
+
+always //
+begin
+ x <= 1;
+ statement();
+end
+
+label : always //
+ x <= 1;
+
+always @ (posedge clk) //
+ x <= 1;
+
+always @ (posedge clk)
+ x <= 1;
+
+always_ff // begin
+ x <= 1;
+
+always_comb
+ x <= 1;
+
+label : always_ff begin
+ begin
+ x <= 1;
+ statement();
+ end
+end
+
+always_ff @ (posedge clk)
+begin
+ x <= 1;
+ statement();
+ foreach (object[i])
+ statement();
+end
+
+always_ff @ (posedge clk)
+begin
+ x <= 1;
+ statement();
+ foreach (object[i])
+ statement();
+end
+
+always_ff @ (posedge clk)
+begin
+ x <= 1;
+ statement();
+ foreach (object[i])
+ statement();
+end
+
+always_ff @ (posedge clk)
+begin
+ x <= 1;
+ statement();
+ foreach (object[i])
+ statement();
+end
+
+always_ff @ (posedge clk)
+begin
+ x <= 1;
+ statement();
+ foreach (object[i])
+ statement();
+end
+
+always_ff @ (posedge clk)
+begin
+ x <= 1;
+ statement();
+ foreach (object[i])
+ statement();
+end
+
+always_ff @ (posedge clk)
+begin
+ x <= 1;
+ statement();
+ foreach (object[i])
+ statement();
+end
+
+always_ff @ (posedge clk)
+begin
+ x <= 1;
+ statement();
+ foreach (object[i])
+ statement();
+end
+
+// always_ff
+// begin
+// x <= 1;
+// end
+
+endmodule
+
+if (condition) begin
+ something();
+end
+else
+ `macro_call()
+
+always : label
+ `macro_call()
+
+begin
+ begin
+ end // always
+ `dont_indent()
+ dont_deindent();
+
+ begin
+ end // foreach()
+ dont_indent();
+ dont_deindent();
+
+ begin
+ end /* while() */
+ dont_indent();
+ dont_deindent();
+end
+
+class a extends b;
+
+ local static function void hello();
+
+ something();
+ endfunction
+
+ constraint l1 {
+ y == 1;
+ }
+
+ constraint l1
+ {
+ y == 1;
+ }
+
+endclass : a
+
+extern module counter (input clk,enable,reset,
+ output logic [3:0] data);
+
+extern module counter2;
+
+class a implements
+ b,
+ c,
+ d;
+
+ function void function_with_multiline_proto(
+ object_type object);
+ indent();
+ endfunction
+
+ function void function_with_multiline_proto(
+ object_type object0,
+ object_type object1,
+ object_type object2,
+ object_type object3
+ );
+ indent();
+ endfunction
+
+endclass
+
+covergroup c1_cg (ref bit x);
+ option.per_instance = 1;
+ type_option.merge_instances = 1;
+
+ x : coverpoint x {
+ bins _0 = {1'h0};
+ bins _1 = {1'h1};
+ }
+
+endgroup
+
+package a;
+
+ class b;
+ endclass
+
+ class c;
+ endclass
+
+ class d;
+ endclass
+
+endpackage
+
+sequence acknowledge
+ ##[1:2] Ack;
+endsequence
+
+property handshake;
+ @(posedge Clock)
+ request |-> acknowledge;
+endproperty
+
+always
+ if(1) begin
+ end
+ // comment
+ else
+ {var0, var1} <= 2'b00;
+
+always
+ if (0) begin
+ var0 <= 1'b0;
+ end else if(0) begin
+ var0 <= 1'b1;
+ end
+
+// comment
+
+virtual class DataTypes_packer#(type T, int L, int W, int I);
+
+ extern static function void unpack(const ref bit [L-1:0] in, ref T out[]);
+ extern static function void unpack5(const ref bit [L-1:0] in, ref t5#(W,I) out[], input int n_MSB2ignore=0);
+
+ /*
+ // packing functions
+ extern static function void pack(const ref T in[], ref bit [L-1:0] out);
+ extern static function void pack2(const ref t2#(W,I) in[], ref bit [L-1:0] out);
+ */
+
+ // unpack functions:
+ extern static function void unpack(const ref bit [L-1:0] in, ref T out[]);
+ extern static function void unpack5(const ref bit [L-1:0] in, ref t5#(W,I) out[], input int n_MSB2ignore=0);
+
+endclass
+
+fork
+ begin
+
+ for(int i=0;i<5;i++) begin
+ automatic int idx=i;
+ fork
+ begin
+ $display("%fns: %0d start",$realtime/1ns,idx);
+ my_seq[idx].go();
+ end
+ join_none
+ end
+
+ // wait for all forks to end
+ wait fork;
+ $display("%fns: all done",$realtime/1ns);
+ end
+join
+
+$display("hi");
+
+assert_value: assert property (@(posedge clk) disable iff (~reset_n)
+ var0 |-> var1 == var2
+);
+
+`ifdef NOTHING
+`endif
+
+wire signal =
+ !var0 && (
+ var2
+ );
+
+task run_phase(uvm_phase phase);
+ int var0 = var1 +
+ var2 *
+ var3;
+
+ int var0 =
+ var1;
+
+ if (map.first(s))
+ do
+ $display("%s : %d\n", s, map[s]);
+ while (map.next(s));
+
+ label : assert(my_seq.randomize());
+ my_seq.start(low_sequencer_h);
+
+ assert(my_seq.randomize() with {Nr==6;});
+ my_seq.start(low_sequencer_h);
+
+ label : assert(my_seq.randomize() with
+ {Nr==6; Time==8;});
+ my_seq.start(low_sequencer_h);
+
+ assert(
+ my_seq.randomize() with
+ );
+
+ //task
+endtask
+
+function void sink_driver::build_phase(uvm_phase phase);
+
+ assert property (prop1)
+ else `uvm_fatal("TAG", "Assertion failed.")
+
+ do_something();
+
+ assert property (prop1)
+ else
+ `uvm_fatal("TAG", "Assertion failed.")
+
+ do_something();
+
+ if (condition)
+ something();
+ else `uvm_fatal("TAG", "This is invalid.")
+
+ do_something();
+
+ if (condition)
+ something();
+ else
+ `uvm_fatal("TAG", "This is invalid.")
+
+ do_something();
+endfunction
+
+// Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/51
+case (XfrState)
+ One_XFR : XfrState_str = "One";
+ Two_XFR : XfrState_str = "Two";
+ End_XFR : XfrState_str = "End";
+ default : XfrState_str = "N/A";
+endcase
+// End of copied code
+
+interface rx_if;
+ logic trans;
+ logic [31:0] data ;
+ logic [31:0] addr ;
+endinterface
+
+generate
+ for (int i = 0; i < 9; ++i) begin : gen_loop
+ dut u_dut(.in(i));
+ end
+endgenerate
+
+program u_prg;
+ logic clk;
+endprogram
+
+// Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/71
+wire a = c <= d &
+ e = f;
+// End of copied code
+
+// Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/72
+function bit return_something();
+ return a &
+ b |
+ c;
+endfunction
+// End of copied code
+
+// Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/80
+/*
+* function text
+* text
+*/
+
+// Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/51
+module dut_wrapper (
+ interface source_IF,
+ interface sink_IF,
+ interface ctrl_IF
+);
+
+endmodule
+// End of copied code
+
+// Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/81
+cover property (
+ a &&
+ b &&
+ c
+);
+// End of copied code
+
+// Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/167
+co__ack_and_req : cover sequence (
+ req && ack
+);
+// End of copied code
+
+// Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/84
+assign out = cond0 ? a :
+ cond1 ? b :
+ c ;
+// End of copied code
+
+// Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/85
+assert_label: assert property (
+ precondition |-> a &&
+ b &&
+ c
+);
+assert_label: assert property (
+ precondition |=> a &&
+ b &&
+ c
+);
+// End of copied code
+
+// Code from: // https://github.com/vhda/verilog_systemverilog.vim/issues/113
+assign a = b <= c &&
+ d <= e &&
+ f <= g &&
+ h <= i;
+// End of copied code
+
+// Code from: // https://github.com/vhda/verilog_systemverilog.vim/issues/129
+if (cond) begin do_something; end
+do_something_else;
+
+// Code from: // https://github.com/vhda/verilog_systemverilog.vim/issues/120
+package automatic regmodel_dpi_pkg;
+ export "DPI-SC" task check_reg;
+ task check_reg(string mystring, output bit [63:0] o1);
+ endtask
+endpackage
+// End of copied code
+
+// vi: set expandtab softtabstop=4 shiftwidth=4:
diff --git a/bundle/verilog/test/indent.sv.html b/bundle/verilog/test/indent.sv.html
new file mode 100644
index 000000000..473e1762d
--- /dev/null
+++ b/bundle/verilog/test/indent.sv.html
@@ -0,0 +1,1081 @@
+
+
+typedef class a;
+
+
+class z;
+
+
+
+ typedef struct {
+ real a;
+ int b;
+ int c;
+ real d; } ts;
+
+ ts s[];
+
+
+
+ typedef struct {
+ real a;
+ int b;
+ int c;
+ real d;
+ } ts2;
+
+ ts2 t[];
+
+ int unsigned cnt=0;
+
+ function new();
+ super.new();
+ endfunction;
+
+ virtual interface my_itf itf;
+
+
+ task run_phase(uvm_phase phase);
+
+ assert(my_seq.randomize());
+ my_seq.start(low_sequencer_h);
+
+ assert(my_seq.randomize() with {Nr==6;});
+ my_seq.start(low_sequencer_h);
+
+ assert(my_seq.randomize() with
+ {Nr==6; Time==8;});
+ my_seq.start(low_sequencer_h);
+
+ assert(
+ my_seq.randomize() with
+ {Nr==6; Time==8;}
+ );
+ my_seq.start(low_sequencer_h);
+
+
+ fork
+ begin : isolating_thread
+ do_something();
+ end : isolating_thread
+ join
+
+
+
+ assert(out>0) else $warning("xxx");
+ $display("Hi");
+
+ assert(out>0)
+ else $warning("xxx");
+ $display("Hi");
+
+ assert(out>0) else $warning("xxx");
+ $display("Hi");
+ $display("Hi");
+
+
+ assert(out>0)
+ else
+ $warning("xxx");
+ $display("Hi");
+
+ if (1 > 0) $display("1 > 0");
+ else $display("1 < 0");
+ $display();
+
+ endtask
+
+
+
+ task run_phase2(uvm_phase phase);
+ assert(out>0) else $warning("xxx");
+ assert(out>0) else $warning("xxx");
+ foreach(out[i]) begin
+ out[i]=new;
+ end
+ endtask
+
+
+
+
+
+
+
+
+
+ task my_seq::body();
+ `uvm_info({get_type_name(),"::body"}, "something" ,UVM_HIGH)
+ req = my_seq_item_REQ::type_id::create("req");
+ endtask
+
+
+
+ pure virtual function void a(input int unsigned N, ref t Data);
+ pure virtual function void b(input int unsigned N, ref t Data);
+ pure virtual function void c(input int unsigned N, ref t Data);
+
+
+
+ function void sink_driver::build_phase(uvm_phase phase);
+ if (!uvm_config_db #(sink_agent_config)::get(this, "", "sink_agent_config", m_cfg) )
+ `uvm_fatal("CONFIG_LOAD", "Cannot get() configuration sink_agent_config from uvm_config_db. Have you set() it?")
+
+ foreach(rand_bool_gen[ch]) begin
+ rand_bool_gen[ch]=new();
+ end
+ endfunction
+
+
+
+ `uvm_info("TAG", "message", UVM_MEDIUM)
+
+ if (condition)
+ `uvm_info("TAG", "message1", UVM_MEDIUM)
+ else
+ `uvm_info("TAG", "message2", UVM_NONE)
+
+
+
+ task fork_test;
+ fork
+ do_something1();
+ do_something2();
+ join_none
+ do_something3();
+ endtask
+
+ task while_one_line;
+ while (1)
+ do_something();
+
+ (* full_case=1 *)
+ (* parallel_case=1 *)
+ case (a)
+ endcase
+
+ (* full_case,
+ parallel_case=1 *)
+ case (a)
+ endcase
+
+ endtask
+
+ function less_or_equal;
+ if (a <= b)
+ less_or_equal = a;
+ endfunction
+
+ task while_block;
+ while (1)
+ begin
+ do_something();
+ end
+ endtask
+
+ task while_block2;
+ while (1) begin
+ do_something();
+ end
+ endtask
+
+ virtual task virtual_task;
+ while (1) begin
+ do_something();
+ end
+ endtask
+
+ virtual function virtual_function;
+ while (1) begin
+ do_something();
+ end
+
+ do
+ do_something();
+ while (1);
+
+ do begin
+ do_something();
+ end while (1);
+
+ endfunction
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ function void hello();
+ foreach (element[i])
+ if (hi)
+ if (hi) begin
+ if (hi) begin
+ foreach (element[i])
+ if (condition0)
+ if (condition1) begin
+ var0 <= 0;
+ end
+ else begin
+ if (1) begin
+ var1 <= 1;
+ something();
+ if (1)
+ if (1) begin
+ something();
+ end
+ else
+ if (1)
+ if (1) begin
+ if (1)
+ something();
+ else begin
+ something();
+ end
+ end
+ else if (1)
+ something();
+ else
+ something();
+
+ if (1)
+ something();
+
+ if (1) begin
+ something();
+ end else
+ something();
+
+ if (1) begin
+ something();
+ end else
+ something();
+
+ if (1)
+
+ case(value)
+ 0,
+ 1:
+ case(value) inside
+ [0:20]:;
+ 21: something();
+ 22:;
+ default: something();
+ endcase
+ 2:;
+ 3:;
+ endcase
+
+ if (1)
+ something();
+
+
+
+ something();
+
+ something();
+ end
+ end
+ deindent_x2_please();
+
+ dont_deindent_please();
+ end
+ deindent_please();
+ end
+ deindent_please();
+ dont_deindent_please();
+ endfunction : hello
+
+ function void hello();
+ if (1)
+ fork
+ something();
+ something();
+ begin
+ something();
+ end
+ begin
+ fork
+ if (1)
+ if (1)
+ if (1) begin
+ something();
+ if (1) begin
+ end
+ something();
+ end
+ something();
+ join
+ if (1)
+ do
+ something();
+ while(1);
+ else
+ do
+ something();
+ while (1) ;
+ something();
+ end
+ if (1)
+ foreach (objects[i])
+ if (1)
+ if (1) begin
+ something();
+ fork begin
+ something();
+ end join
+ end
+ something();
+ join_none
+
+
+ fork
+ p1: begin
+ myvar=1'b1;
+ `info("some message with the word join");
+ end
+ p2: begin
+ myvar2=1'b1;
+ end
+ join
+
+ endfunction : hello
+
+ local static function void hello();
+ const bit variable1 =
+ func_call(object_t) && structue_t.field_t.source != ENUM_VALUE &&
+ object_t.field_t && variable0;
+
+ const bit variable1 =
+ func_call(object_t) && structue_t.field_t.source != ENUM_VALUE
+ && object_t.field_t && variable0;
+
+ const bit variable2 =
+ object_t.field_t && object_t.field_t.source == ENUM_VALUE;
+
+ bit variable3;
+
+
+ if (variable && variable && variable &&
+ variable)
+ indent();
+
+ de_indent();
+
+
+ if (variable && variable && variable
+ && variable
+ && variable) begin
+ indent();
+ stay();
+ end
+
+ de_indent();
+
+ variable = variable
+ || variable || variable;
+
+ variable = variable ||
+ variable || variable;
+
+ variable = (variable == CONSTANT) &
+ variable &
+ variable;
+
+ wire var0 = a &
+ b;
+
+ wire [1:0] var1 = a &
+ b;
+
+ var2[0] = a &
+ b;
+
+ {var0, var1} = a &
+ b;
+
+ some_struct.field1 = a &
+ b;
+
+ some_type #(params) some_object = cond0 ? a :
+ cond1 ? b : c;
+
+ if (1) begin
+ if (1
+ && 1)
+ something();
+ end
+
+ endfunction
+
+endclass
+
+class a;
+ class nested;
+ import "DPI-C" function void c_print();
+ int b;
+ endclass
+endclass
+
+clocking ck1 @(posedge clk);
+ default input #1step output negedge;
+ input a;
+ output y;
+endclocking
+
+TODO
+
+
+
+
+
+virtual class base;
+
+ extern function void x(input int unsigned N, ref t Data);
+ extern function void y(input int unsigned N, ref t Data);
+
+ pure virtual function void a(input int unsigned N, ref t Data);
+ pure virtual function void b(input int unsigned N, ref t Data);
+ pure virtual function void c(input int unsigned N, ref t Data);
+
+endclass;
+
+
+
+module MyModule #(
+ parameter A = 1,
+ parameter B = 2
+)(
+ input I,
+ output O
+);
+
+
+wire Val_IP = !In_Pkt_S_Bus_enf ||
+ ((Pls_Don || ResVal) && (Pls_Res || ResFnd));
+
+wire Val_IP =
+ !In_Pkt_S_Bus_enf ||
+ ((Pls_Don || ResVal) && (Pls_Res || ResFnd));
+
+wire Val_IP = !In_Pkt_S_Bus_enf ?
+ ((Pls_Don || ResVal) && (Pls_Res == ResFnd)) :
+ ((Pls_Don || ResVal) && (Pls_Res || ResFnd));
+
+MyModule #(
+ .A (1),
+ .B (2)
+) Module_1 (
+ .I (wire1),
+ .O (wire2)
+);
+
+or or_0();
+
+endmodule
+
+
+
+case (Signal)
+ 2'd0: begin Result <= 0; end
+ 2'd1: begin Result <= 1; end
+ 2'd2: begin Result <= 2; end
+ default: begin Result <= 0; end
+endcase
+
+
+interface class base;
+
+ pure virtual function void a(input int unsigned N, ref t Data);
+ pure virtual function void b(input int unsigned N, ref t Data);
+ pure virtual function void c(input int unsigned N, ref t Data);
+
+endclass;
+
+module m #(1)
+(
+ portA,
+ portB
+);
+
+
+module a;
+endmodule
+
+endmodule
+
+module m (
+ portA,
+ portB
+);
+
+device d0 (
+ .port (port[1]),
+ .port2(),
+ .portA(port[2])
+);
+
+
+device d1 (
+ .port (port[1]),
+
+ .*
+);
+
+`ifdef DO_THIS
+ device d1 (
+ .port (port[1]),
+
+
+ .port2(),
+ .*
+ );
+`endif
+
+`ifdef DO_THIS
+ device2 d2 (
+ .out,
+ .a,
+ .b(B)
+TODO
+ );
+`endif
+
+
+device d1 (
+ .port (port[1]),
+
+ .port2(),
+
+
+ .portA(port[2])
+);
+
+`define VALUE 3
+
+`define VALUE_MULTI_LINE \
+ 16'hFF
+
+`ifdef V95
+ device d2 ( out, portA, portB );
+ device d2 ( out, portA, portB );
+ `ifdef V95
+ device d2 ( out, portA, portB );
+ device d2 ( out, portA, portB );
+ `endif
+`elsif V2K
+ device d2 ( .out(out), .* );
+ device d2 ( out, portA, portB );
+ `ifndef SWAP
+ device d3 ( .out(out), .* );
+ device d2 ( .out(out), .* );
+ `else
+ device d3 ( .out(out), .portA(portB), .portB(portA) );
+ device d2 ( .out(out), .* );
+ `endif
+`endif
+`ifndef SWAP
+ device d3 ( .out(out), .* );
+ device d2 ( .out(out), .* );
+`else
+ device d3 ( .out(out), .portA(portB), .portB(portA) );
+ device d2 ( .out(out), .* );
+`endif
+
+endmodule
+
+class a;
+endclass : a
+
+module a import some_pkg::*;
+(
+ input clk,
+ output x
+);
+
+always @ (posedge clk)
+begin
+end
+
+always
+ x <= 1;
+
+always
+begin
+ x <= 1;
+ statement();
+end
+
+always
+begin
+ x <= 1;
+ statement();
+end
+
+label : always
+ x <= 1;
+
+always @ (posedge clk)
+ x <= 1;
+
+always @ (posedge clk)
+ x <= 1;
+
+always_ff
+ x <= 1;
+
+always_comb
+ x <= 1;
+
+label : always_ff begin
+ begin
+ x <= 1;
+ statement();
+ end
+end
+
+always_ff @ (posedge clk)
+begin
+ x <= 1;
+ statement();
+ foreach (object[i])
+ statement();
+end
+
+always_ff @ (posedge clk)
+begin
+ x <= 1;
+ statement();
+ foreach (object[i])
+ statement();
+end
+
+always_ff @ (posedge clk)
+begin
+ x <= 1;
+ statement();
+ foreach (object[i])
+ statement();
+end
+
+always_ff @ (posedge clk)
+begin
+ x <= 1;
+ statement();
+ foreach (object[i])
+ statement();
+end
+
+always_ff @ (posedge clk)
+begin
+ x <= 1;
+ statement();
+ foreach (object[i])
+ statement();
+end
+
+always_ff @ (posedge clk)
+begin
+ x <= 1;
+ statement();
+ foreach (object[i])
+ statement();
+end
+
+always_ff @ (posedge clk)
+begin
+ x <= 1;
+ statement();
+ foreach (object[i])
+ statement();
+end
+
+always_ff @ (posedge clk)
+begin
+ x <= 1;
+ statement();
+ foreach (object[i])
+ statement();
+end
+
+
+
+
+
+
+endmodule
+
+if (condition) begin
+ something();
+end
+else
+ `macro_call()
+
+always : label
+ `macro_call()
+
+begin
+ begin
+ end
+ `dont_indent()
+ dont_deindent();
+
+ begin
+ end
+ dont_indent();
+ dont_deindent();
+
+ begin
+ end
+ dont_indent();
+ dont_deindent();
+end
+
+class a extends b;
+
+ local static function void hello();
+
+ something();
+ endfunction
+
+ constraint l1 {
+ y == 1;
+ }
+
+ constraint l1
+ {
+ y == 1;
+ }
+
+endclass : a
+
+extern module counter (input clk,enable,reset,
+ output logic [3:0] data);
+
+extern module counter2;
+
+class a implements
+ b,
+ c,
+ d;
+
+ function void function_with_multiline_proto(
+ object_type object);
+ indent();
+ endfunction
+
+ function void function_with_multiline_proto(
+ object_type object0,
+ object_type object1,
+ object_type object2,
+ object_type object3
+ );
+ indent();
+ endfunction
+
+endclass
+
+covergroup c1_cg (ref bit x);
+ option.per_instance = 1;
+ type_option.merge_instances = 1;
+
+ x : coverpoint x {
+ bins _0 = {1'h0};
+ bins _1 = {1'h1};
+ }
+
+endgroup
+
+package a;
+
+ class b;
+ endclass
+
+ class c;
+ endclass
+
+ class d;
+ endclass
+
+endpackage
+
+sequence acknowledge
+ ##[1:2] Ack;
+endsequence
+
+property handshake;
+ @(posedge Clock)
+ request |-> acknowledge;
+endproperty
+
+always
+ if(1) begin
+ end
+
+ else
+ {var0, var1} <= 2'b00;
+
+always
+ if (0) begin
+ var0 <= 1'b0;
+ end else if(0) begin
+ var0 <= 1'b1;
+ end
+
+
+
+virtual class DataTypes_packer#(type T, int L, int W, int I);
+
+ extern static function void unpack(const ref bit [L-1:0] in, ref T out[]);
+ extern static function void unpack5(const ref bit [L-1:0] in, ref t5#(W,I) out[], input int n_MSB2ignore=0);
+
+
+
+
+
+
+
+
+ extern static function void unpack(const ref bit [L-1:0] in, ref T out[]);
+ extern static function void unpack5(const ref bit [L-1:0] in, ref t5#(W,I) out[], input int n_MSB2ignore=0);
+
+endclass
+
+fork
+ begin
+
+ for(int i=0;i<5;i++) begin
+ automatic int idx=i;
+ fork
+ begin
+ $display("%fns: %0d start",$realtime/1ns,idx);
+ my_seq[idx].go();
+ end
+ join_none
+ end
+
+
+ wait fork;
+ $display("%fns: all done",$realtime/1ns);
+ end
+join
+
+$display("hi");
+
+assert_value: assert property (@(posedge clk) disable iff (~reset_n)
+ var0 |-> var1 == var2
+);
+
+`ifdef NOTHING
+`endif
+
+wire signal =
+ !var0 && (
+ var2
+ );
+
+task run_phase(uvm_phase phase);
+ int var0 = var1 +
+ var2 *
+ var3;
+
+ int var0 =
+ var1;
+
+ if (map.first(s))
+ do
+ $display("%s : %d\n", s, map[s]);
+ while (map.next(s));
+
+ label : assert(my_seq.randomize());
+ my_seq.start(low_sequencer_h);
+
+ assert(my_seq.randomize() with {Nr==6;});
+ my_seq.start(low_sequencer_h);
+
+ label : assert(my_seq.randomize() with
+ {Nr==6; Time==8;});
+ my_seq.start(low_sequencer_h);
+
+ assert(
+ my_seq.randomize() with
+ );
+
+
+endtask
+
+function void sink_driver::build_phase(uvm_phase phase);
+
+ assert property (prop1)
+ else `uvm_fatal("TAG", "Assertion failed.")
+
+ do_something();
+
+ assert property (prop1)
+ else
+ `uvm_fatal("TAG", "Assertion failed.")
+
+ do_something();
+
+ if (condition)
+ something();
+ else `uvm_fatal("TAG", "This is invalid.")
+
+ do_something();
+
+ if (condition)
+ something();
+ else
+ `uvm_fatal("TAG", "This is invalid.")
+
+ do_something();
+endfunction
+
+
+case (XfrState)
+ One_XFR : XfrState_str = "One";
+ Two_XFR : XfrState_str = "Two";
+ End_XFR : XfrState_str = "End";
+ default : XfrState_str = "N/A";
+endcase
+
+
+interface rx_if;
+ logic trans;
+ logic [31:0] data ;
+ logic [31:0] addr ;
+endinterface
+
+generate
+ for (int i = 0; i < 9; ++i) begin : gen_loop
+ dut u_dut(.in(i));
+ end
+endgenerate
+
+program u_prg;
+ logic clk;
+endprogram
+
+
+wire a = c <= d &
+ e = f;
+
+
+
+function bit return_something();
+ return a &
+ b |
+ c;
+endfunction
+
+
+
+
+
+
+
+
+
+module dut_wrapper (
+ interface source_IF,
+ interface sink_IF,
+ interface ctrl_IF
+);
+
+endmodule
+
+
+
+cover property (
+ a &&
+ b &&
+ c
+);
+
+
+
+co__ack_and_req : cover sequence (
+ req && ack
+);
+
+
+
+assign out = cond0 ? a :
+ cond1 ? b :
+ c ;
+
+
+
+assert_label: assert property (
+ precondition |-> a &&
+ b &&
+ c
+);
+assert_label: assert property (
+ precondition |=> a &&
+ b &&
+ c
+);
+
+
+
+assign a = b <= c &&
+ d <= e &&
+ f <= g &&
+ h <= i;
+
+
+
+if (cond) begin do_something; end
+do_something_else;
+
+
+package automatic regmodel_dpi_pkg;
+ export "DPI-SC" task check_reg;
+ task check_reg(string mystring, output bit [63:0] o1);
+ endtask
+endpackage
+
+
+
+
+
diff --git a/bundle/verilog/test/mod.sv b/bundle/verilog/test/mod.sv
new file mode 100644
index 000000000..50e058144
--- /dev/null
+++ b/bundle/verilog/test/mod.sv
@@ -0,0 +1,52 @@
+module mod(
+ input wire [7:0] in1,
+ input wire in2,
+ output reg out
+);
+parameter PARAM1 = 1;
+parameter PARAM2 = 2;
+
+function test(
+ input a,
+ input b,
+ output z
+);
+endfunction
+
+endmodule
+
+class myclass #(
+ type BASE = extended_base ,
+ int size = 1
+) extends BASE;
+ logic value_myclass;
+ real rl_variable = 1.0;
+
+ function method(input a, input b);
+ endfunction : method
+
+ task atask(input a, output x);
+ endtask : atask
+
+endclass : myclass
+
+class extended_base extends base;
+ logic value_extended_base;
+
+ function method(input a, input b);
+ endfunction : method
+
+ task btask(input a, output x);
+ endtask : atask
+
+endclass : extended_base
+
+class base;
+ logic value_base;
+
+ task ctask(input x, output z);
+ endtask : ctask
+
+endclass : base
+
+// vi: set expandtab softtabstop=4 shiftwidth=4:
diff --git a/bundle/verilog/test/run_test.vim b/bundle/verilog/test/run_test.vim
new file mode 100644
index 000000000..56084b41b
--- /dev/null
+++ b/bundle/verilog/test/run_test.vim
@@ -0,0 +1,180 @@
+"-----------------------------------------------------------------------
+" Global configurations
+"-----------------------------------------------------------------------
+" Configure custom syntax
+let g:verilog_syntax_custom = {
+ \ 'spyglass' : [{
+ \ 'match_start' : '\/\/\s*spyglass\s\+disable_block\s\+\z(\(\w\|-\)\+\(\s\+\(\w\|-\)\+\)*\)',
+ \ 'match_end' : '\/\/\s*spyglass\s\+enable_block\s\+\z1',
+ \ 'syn_argument': 'transparent keepend',
+ \ }],
+ \ }
+
+"-----------------------------------------------------------------------
+" Syntax folding test
+"-----------------------------------------------------------------------
+function! RunTestFold()
+ let test_result=0
+
+ " Enable all syntax folding
+ let g:verilog_syntax_fold_lst="all"
+ set foldmethod=syntax
+ set noautochdir
+
+ " Open syntax fold test file in read-only mode
+ silent view test/folding.v
+
+ " Verify folding
+ let test_result=TestFold(0) || test_result
+ echo ''
+
+ " Test with "block_nested"
+ let g:verilog_syntax_fold_lst="all,block_nested"
+ silent view!
+ let test_result=TestFold(1) || test_result
+ echo ''
+
+ " Test with "block_named"
+ let g:verilog_syntax_fold_lst="all,block_named"
+ silent view!
+ let test_result=TestFold(2) || test_result
+ echo ''
+
+ " Check test results and exit accordingly
+ if test_result
+ cquit
+ else
+ qall!
+ endif
+endfunction
+
+"-----------------------------------------------------------------------
+" Syntax indent test
+"-----------------------------------------------------------------------
+function! RunTestIndent()
+ let g:verilog_disable_indent_lst = "module,eos"
+ let test_result=0
+
+ " Open syntax indent test file
+ silent edit test/indent.sv
+
+ " Verify indent
+ let test_result=TestIndent() || test_result
+ echo ''
+ silent edit!
+
+ " Test again with 'ignorecase' enabled
+ setlocal ignorecase
+ let test_result=TestIndent() || test_result
+ echo ''
+ silent edit!
+
+ " Make file read-only to guarantee that vim quits with exit status 0
+ silent view!
+
+ " Check test results and exit accordingly
+ if test_result
+ cquit
+ else
+ qall!
+ endif
+endfunction
+
+"-----------------------------------------------------------------------
+" Error format test
+"-----------------------------------------------------------------------
+function! RunTestEfm()
+ let test_result=0
+
+ set nomore "Disable pager to avoid issues with Travis
+
+ let g:verilog_efm_quickfix_clean = 1
+
+ for check_uvm in [0, 1]
+ if check_uvm
+ let g:verilog_efm_uvm_lst = 'all'
+ else
+ unlet! g:verilog_efm_uvm_lst
+ endif
+
+ let test_result = TestEfm('iverilog', 1, check_uvm) || test_result
+ let test_result = TestEfm('verilator', 1, check_uvm) || test_result
+ let test_result = TestEfm('verilator', 3, check_uvm) || test_result
+ let test_result = TestEfm('ncverilog', 1, check_uvm) || test_result
+ let test_result = TestEfm('ncverilog', 3, check_uvm) || test_result
+ let test_result = TestEfm('spyglass', 1, check_uvm) || test_result
+ endfor
+
+ " Check test results and exit accordingly
+ if test_result
+ cquit
+ else
+ qall!
+ endif
+endfunction
+
+"-----------------------------------------------------------------------
+" Syntax test
+"-----------------------------------------------------------------------
+function! RunTestSyntax()
+ let test_result=0
+
+ set nomore "Disable pager to avoid issues with Travis
+ set foldmethod=syntax
+ set foldlevel=99
+
+ " Run syntax test for various folding configurations
+ let g:verilog_syntax_fold_lst=''
+ let test_result = TestSyntax('syntax.sv', g:verilog_syntax_fold_lst) || test_result
+
+ let g:verilog_syntax_fold_lst='all'
+ let test_result = TestSyntax('syntax.sv', g:verilog_syntax_fold_lst) || test_result
+
+ let g:verilog_syntax_fold_lst='all,block_nested'
+ let test_result = TestSyntax('syntax.sv', g:verilog_syntax_fold_lst) || test_result
+
+ let g:verilog_syntax_fold_lst='all,block_named'
+ let test_result = TestSyntax('syntax.sv', g:verilog_syntax_fold_lst) || test_result
+
+ let g:verilog_syntax_fold_lst='all,instance'
+ let test_result = TestSyntax('syntax.sv', g:verilog_syntax_fold_lst) || test_result
+
+ let g:verilog_syntax_fold_lst=''
+ let test_result = TestSyntax('folding.v', g:verilog_syntax_fold_lst) || test_result
+
+ let g:verilog_syntax_fold_lst='all'
+ let test_result = TestSyntax('folding.v', g:verilog_syntax_fold_lst) || test_result
+
+ let g:verilog_syntax_fold_lst='all,block_nested'
+ let test_result = TestSyntax('folding.v', g:verilog_syntax_fold_lst) || test_result
+
+ let g:verilog_syntax_fold_lst='all,block_named'
+ let test_result = TestSyntax('folding.v', g:verilog_syntax_fold_lst) || test_result
+
+ let g:verilog_syntax_fold_lst='all,instance'
+ let test_result = TestSyntax('folding.v', g:verilog_syntax_fold_lst) || test_result
+
+ let g:verilog_syntax_fold_lst=''
+ let test_result = TestSyntax('indent.sv', g:verilog_syntax_fold_lst) || test_result
+
+ let g:verilog_syntax_fold_lst='all'
+ let test_result = TestSyntax('indent.sv', g:verilog_syntax_fold_lst) || test_result
+
+ let g:verilog_syntax_fold_lst='all,block_nested'
+ let test_result = TestSyntax('indent.sv', g:verilog_syntax_fold_lst) || test_result
+
+ let g:verilog_syntax_fold_lst='all,block_named'
+ let test_result = TestSyntax('indent.sv', g:verilog_syntax_fold_lst) || test_result
+
+ let g:verilog_syntax_fold_lst='all,instance'
+ let test_result = TestSyntax('indent.sv', g:verilog_syntax_fold_lst) || test_result
+
+ " Check test results and exit accordingly
+ if test_result
+ cquit
+ else
+ qall!
+ endif
+endfunction
+
+" vi: set expandtab softtabstop=4 shiftwidth=4:
diff --git a/bundle/verilog/test/syntax.sv b/bundle/verilog/test/syntax.sv
new file mode 100644
index 000000000..78add7b86
--- /dev/null
+++ b/bundle/verilog/test/syntax.sv
@@ -0,0 +1,393 @@
+module #(
+ parameter TEST1 = $clog(0),
+ parameter TEST2 = $clog(1),
+ parameter TEST3 = $clog(2)
+) mymodule(
+ input wire a,
+ input wire b,
+ `ifdef MACRO
+ input wire c,
+ `endif
+ output wire y
+);
+
+ othermodule #(.something (a),
+ .somethingelse(b)
+ ) inst(.p1(), .p2(), .p3 (),
+ .p4(),
+ .p5(), .p6(), .p7(),
+ .p8 ()
+ .p9 (a)
+ );
+
+ mymod MOD(.IN1(), .IN2(), .OP(),
+ .OUT());
+
+endmodule
+
+`define DEF_WITH_EQ = 1'b0
+`define DEF_MULTI_LINE cond(a,b,c) \
+ a ? b : c
+
+`ifdef SYSTEM_VERILOG_KEYWORDS
+accept_on
+alias
+always
+always_comb
+always_ff
+always_latch
+and
+assert
+assign
+assume
+automatic
+before
+begin
+end
+bind
+bins
+binsof
+bit
+break
+buf
+bufif0
+bufif1
+byte
+case
+casex
+casez
+cell
+chandle
+checker
+cmos
+config
+const
+constraint
+context
+continue
+cover
+coverpoint
+cross
+deassign
+default
+defparam
+design
+disable
+dist
+do
+edge
+else
+endcase
+endchecker
+endconfig
+endgenerate
+endpackage
+endprimitive
+endprogram
+endtable
+enum
+event
+eventually
+expect
+export "DPI-SC" task exported_task;
+extends
+extern
+final
+first_match
+for
+force
+foreach
+forever
+fork
+forkjoin
+generate
+genvar
+global
+highz0
+highz1
+if
+iff
+ifnone
+ignore_bins
+illegal_bins
+implements
+implies
+import
+incdir
+include
+initial
+inout
+input
+inside
+instance
+int
+integer
+interconnect
+intersect
+join
+join_any
+join_none
+large
+let
+liblist
+library
+local
+localparam
+logic
+longint
+macromodule
+mailbox
+matches
+medium
+modport
+nand
+negedge
+nettype
+new
+nexttime
+nmos
+nor
+noshowcancelled
+not
+notif0
+notif1
+null
+or
+output
+package
+packed
+parameter
+pmos
+posedge
+primitive
+priority
+program
+protected
+pull0
+pull1
+pulldown
+pullup
+pulsestyle_ondetect
+pulsestyle_onevent
+pure
+rand
+randc
+randcase
+randsequence
+rcmos
+real
+realtime
+ref
+reg
+reject_on
+release
+repeat
+restrict
+return
+rnmos
+rpmos
+rtran
+rtranif0
+rtranif1
+s_always
+s_eventually
+s_nexttime
+s_until
+s_until_with
+scalared
+semaphore
+shortint
+shortreal
+showcancelled
+signed
+small
+soft
+solve
+specparam
+static
+string
+strong
+strong0
+strong1
+struct
+super
+supply0
+supply1
+sync_accept_on
+sync_reject_on
+table
+tagged
+this
+throughout
+time
+timeprecision
+timeunit
+tran
+tranif0
+tranif1
+tri
+tri0
+tri1
+triand
+trior
+trireg
+type
+union
+unique
+unique0
+unsigned
+until
+until_with
+untyped
+use
+uwire
+var
+vectored
+virtual
+void
+wait
+wait_order
+wand
+weak
+weak0
+weak1
+while
+wildcard
+wire
+with
+within
+wor
+xnor
+xor
+// Syntax regions
+typedef;
+class
+endclass
+clocking
+endclocking
+covergroup
+endgroup
+function
+endfunction
+interface
+endinterface
+module
+endmodule
+property
+endproperty
+sequence
+endsequence
+specify
+endspecify
+task
+endtask
+`endif
+`ifdef COMPLEX_STATEMENTS
+typedef class c;
+`endif
+`ifdef TIME
+10ns
+100ns
+1ps
+2_0ps
+3_000_000s
+1.23ns
+1_000.123ns
+10_000.123ns
+100_000.123ns
+1_000_000.123ns
+1.2.3ns // Second to should not be part of number syntax
+1step
+`endif
+`ifdef NUMBERS
+4'h0
+4'h1
+4'h2
+4'h3
+4'h4
+4'h5
+4'h6
+4'h7
+4'h8
+4'h9
+4'ha
+4'hb
+4'hc
+4'hd
+4'he
+4'hf
+4'hA
+4'hB
+4'hC
+4'hD
+4'hE
+4'hF
+4'hg // Invalid value for hexadecimal number
+4'hG // Invalid value for hexadecimal number
+3'o0
+3'o1
+3'o2
+3'o3
+3'o4
+3'o5
+3'o6
+3'o7
+3'o8 // Invalid value for octal number
+3'b0_01
+3'b001
+3'b_01
+3'b120 // Invalid value for binary number
+'d10000
+'d_000_000
+'d_x00_000
+4'b0?x0
+4'b010?
+4'b010? ? 4'b????; // Conditional '?' and ';' should not be part of number syntax
+`endif
+// synopsys
+
+/* synopsys dc_script_begin
+* set_size_only {U1}
+* synopsys dc_script_end
+*/
+
+// synopsys dc_script_begin
+// set_size_only {U1}
+// synopsys dc_script_end
+
+// TODO todo check
+
+/*
+* TODO todo check
+*/
+
+/*//my comment */
+
+//my /*comment*/
+
+// Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/186
+string foo = "bar, baz";
+int foo2 = 0;
+// End of copied code
+
+// Comment with DEFINE-ML
+
+always@(posedge clk or posedge rst)
+begin
+ priority if (rst)
+ state <= IDLE;
+ else
+ state <= NS;
+end
+
+always @(*) begin : label
+ if (a) begin
+ y = c, z = a;
+ end else begin
+ y = d, z = b;
+ end
+end
+
+assign a = myfunc(this);
+
+// vi: set expandtab softtabstop=4 shiftwidth=4:
diff --git a/bundle/verilog/test/syntax.sv.html b/bundle/verilog/test/syntax.sv.html
new file mode 100644
index 000000000..c2a55007c
--- /dev/null
+++ b/bundle/verilog/test/syntax.sv.html
@@ -0,0 +1,397 @@
+
+
+module #(
+ parameter TEST1 = $clog(0),
+ parameter TEST2 = $clog(1),
+ parameter TEST3 = $clog(2)
+) mymodule(
+ input wire a,
+ input wire b,
+ `ifdef MACRO
+ input wire c,
+ `endif
+ output wire y
+);
+
+ othermodule #(.something (a),
+ .somethingelse(b)
+ ) inst(.p1(), .p2(), .p3 (),
+ .p4(),
+ .p5(), .p6(), .p7(),
+ .p8 ()
+ .p9 (a)
+ );
+
+ mymod MOD(.IN1(), .IN2(), .OP(),
+ .OUT());
+
+endmodule
+
+`define DEF_WITH_EQ = 1'b0
+`define DEF_MULTI_LINE cond(a,b,c) \
+ a ? b : c
+
+`ifdef SYSTEM_VERILOG_KEYWORDS
+accept_on
+alias
+always
+always_comb
+always_ff
+always_latch
+and
+assert
+assign
+assume
+automatic
+before
+begin
+end
+bind
+bins
+binsof
+bit
+break
+buf
+bufif0
+bufif1
+byte
+case
+casex
+casez
+cell
+chandle
+checker
+cmos
+config
+const
+constraint
+context
+continue
+cover
+coverpoint
+cross
+deassign
+default
+defparam
+design
+disable
+dist
+do
+edge
+else
+endcase
+endchecker
+endconfig
+endgenerate
+endpackage
+endprimitive
+endprogram
+endtable
+enum
+event
+eventually
+expect
+export "DPI-SC" task exported_task;
+extends
+extern
+final
+first_match
+for
+force
+foreach
+forever
+fork
+forkjoin
+generate
+genvar
+global
+highz0
+highz1
+if
+iff
+ifnone
+ignore_bins
+illegal_bins
+implements
+implies
+import
+incdir
+include
+initial
+inout
+input
+inside
+instance
+int
+integer
+interconnect
+intersect
+join
+join_any
+join_none
+large
+let
+liblist
+library
+local
+localparam
+logic
+longint
+macromodule
+mailbox
+matches
+medium
+modport
+nand
+negedge
+nettype
+new
+nexttime
+nmos
+nor
+noshowcancelled
+not
+notif0
+notif1
+null
+or
+output
+package
+packed
+parameter
+pmos
+posedge
+primitive
+priority
+program
+protected
+pull0
+pull1
+pulldown
+pullup
+pulsestyle_ondetect
+pulsestyle_onevent
+pure
+rand
+randc
+randcase
+randsequence
+rcmos
+real
+realtime
+ref
+reg
+reject_on
+release
+repeat
+restrict
+return
+rnmos
+rpmos
+rtran
+rtranif0
+rtranif1
+s_always
+s_eventually
+s_nexttime
+s_until
+s_until_with
+scalared
+semaphore
+shortint
+shortreal
+showcancelled
+signed
+small
+soft
+solve
+specparam
+static
+string
+strong
+strong0
+strong1
+struct
+super
+supply0
+supply1
+sync_accept_on
+sync_reject_on
+table
+tagged
+this
+throughout
+time
+timeprecision
+timeunit
+tran
+tranif0
+tranif1
+tri
+tri0
+tri1
+triand
+trior
+trireg
+type
+union
+unique
+unique0
+unsigned
+until
+until_with
+untyped
+use
+uwire
+var
+vectored
+virtual
+void
+wait
+wait_order
+wand
+weak
+weak0
+weak1
+while
+wildcard
+wire
+with
+within
+wor
+xnor
+xor
+
+typedef;
+class
+endclass
+clocking
+endclocking
+covergroup
+endgroup
+function
+endfunction
+interface
+endinterface
+module
+endmodule
+property
+endproperty
+sequence
+endsequence
+specify
+endspecify
+task
+endtask
+`endif
+`ifdef COMPLEX_STATEMENTS
+typedef class c;
+`endif
+`ifdef TIME
+10ns
+100ns
+1ps
+2_0ps
+3_000_000s
+1.23ns
+1_000.123ns
+10_000.123ns
+100_000.123ns
+1_000_000.123ns
+1.2.3ns
+1step
+`endif
+`ifdef NUMBERS
+4'h0
+4'h1
+4'h2
+4'h3
+4'h4
+4'h5
+4'h6
+4'h7
+4'h8
+4'h9
+4'ha
+4'hb
+4'hc
+4'hd
+4'he
+4'hf
+4'hA
+4'hB
+4'hC
+4'hD
+4'hE
+4'hF
+4'hg
+4'hG
+3'o0
+3'o1
+3'o2
+3'o3
+3'o4
+3'o5
+3'o6
+3'o7
+3'o8
+3'b0_01
+3'b001
+3'b_01
+3'b120
+'d10000
+'d_000_000
+'d_x00_000
+4'b0?x0
+4'b010?
+4'b010? ? 4'b????;
+`endif
+// synopsys
+
+/* synopsys dc_script_begin
+* set_size_only {U1}
+* synopsys dc_script_end
+*/
+
+// synopsys dc_script_begin
+// set_size_only {U1}
+// synopsys dc_script_end
+
+TODO
+
+
+TODO
+
+
+
+
+
+
+
+string foo = "bar, baz";
+int foo2 = 0;
+
+
+
+
+always@(posedge clk or posedge rst)
+begin
+ priority if (rst)
+ state <= IDLE;
+ else
+ state <= NS;
+end
+
+always @(*) begin : label
+ if (a) begin
+ y = c, z = a;
+ end else begin
+ y = d, z = b;
+ end
+end
+
+assign a = myfunc(this);
+
+
+
+
diff --git a/bundle/verilog/test/test.v b/bundle/verilog/test/test.v
new file mode 100644
index 000000000..25a3c3f2e
--- /dev/null
+++ b/bundle/verilog/test/test.v
@@ -0,0 +1,77 @@
+module test1;
+
+reg test;
+
+ test.
+test.
+
+mod #(
+ .TEST (1)
+) test(
+ .port1 (test),
+ .
+);
+
+mod test(
+ .port1 (test),
+ .
+);
+
+mod
+test(
+ .port1 (test),
+ .
+);
+
+ mod #(
+ .TEST (1)
+) test(
+ .port1 (test),
+ .
+);
+
+ mod test(
+ .port1 (test),
+ .port2 (bus[(3-1):0]),
+ .port3 (test),
+ .in1 (in1),
+ .
+);
+
+ mod
+ test(
+ .port1 (test),
+ .
+);
+
+ola = test.
+
+mod u_mod1 (
+ .
+);
+endmodule
+
+class test2 #(type T=base);
+
+myclass #(type BASE=base) object;
+myclass object_with_long_name;
+myclass obj;
+T typeclass;
+
+object.method(
+ .
+);
+
+object.atask(.);
+
+object.
+
+object_with_long_name.
+
+obj.
+
+typeclass.
+
+endclass
+
+// vi: set expandtab softtabstop=4 shiftwidth=4:
diff --git a/bundle/verilog/test/test_vimrc b/bundle/verilog/test/test_vimrc
new file mode 100644
index 000000000..1b0ad741d
--- /dev/null
+++ b/bundle/verilog/test/test_vimrc
@@ -0,0 +1,5 @@
+set nocompatible
+set modeline
+set noswapfile
+filetype plugin indent on
+syntax enable
diff --git a/doc/SpaceVim.txt b/doc/SpaceVim.txt
index 9de3ef3bc..e3232632d 100644
--- a/doc/SpaceVim.txt
+++ b/doc/SpaceVim.txt
@@ -202,27 +202,28 @@ CONTENTS *SpaceVim-contents*
109. lang#v.....................................|SpaceVim-layers-lang-v|
110. lang#vala...............................|SpaceVim-layers-lang-vala|
111. lang#vbnet.............................|SpaceVim-layers-lang-vbnet|
- 112. lang#vim.................................|SpaceVim-layers-lang-vim|
- 113. lang#vue.................................|SpaceVim-layers-lang-vue|
- 114. lang#wdl.................................|SpaceVim-layers-lang-wdl|
- 115. lang#wolfram.........................|SpaceVim-layers-lang-wolfram|
- 116. lang#xml.................................|SpaceVim-layers-lang-xml|
- 117. lang#xquery...........................|SpaceVim-layers-lang-xquery|
- 118. lang#zig.................................|SpaceVim-layers-lang-zig|
- 119. language server protocol......................|SpaceVim-layers-lsp|
- 120. leaderf...................................|SpaceVim-layers-leaderf|
- 121. mail.........................................|SpaceVim-layers-mail|
- 122. operator.................................|SpaceVim-layers-operator|
- 123. shell.......................................|SpaceVim-layers-shell|
- 124. ssh...........................................|SpaceVim-layers-ssh|
- 125. test.........................................|SpaceVim-layers-test|
- 126. tmux.........................................|SpaceVim-layers-tmux|
- 127. tools#dash.............................|SpaceVim-layers-tools-dash|
- 128. tools#mpv...............................|SpaceVim-layers-tools-mpv|
- 129. tools#zeal.............................|SpaceVim-layers-tools-zeal|
- 130. treesitter.............................|SpaceVim-layers-treesitter|
- 131. ui.............................................|SpaceVim-layers-ui|
- 132. unite.......................................|SpaceVim-layers-unite|
+ 112. lang#verilog.........................|SpaceVim-layers-lang-verilog|
+ 113. lang#vim.................................|SpaceVim-layers-lang-vim|
+ 114. lang#vue.................................|SpaceVim-layers-lang-vue|
+ 115. lang#wdl.................................|SpaceVim-layers-lang-wdl|
+ 116. lang#wolfram.........................|SpaceVim-layers-lang-wolfram|
+ 117. lang#xml.................................|SpaceVim-layers-lang-xml|
+ 118. lang#xquery...........................|SpaceVim-layers-lang-xquery|
+ 119. lang#zig.................................|SpaceVim-layers-lang-zig|
+ 120. language server protocol......................|SpaceVim-layers-lsp|
+ 121. leaderf...................................|SpaceVim-layers-leaderf|
+ 122. mail.........................................|SpaceVim-layers-mail|
+ 123. operator.................................|SpaceVim-layers-operator|
+ 124. shell.......................................|SpaceVim-layers-shell|
+ 125. ssh...........................................|SpaceVim-layers-ssh|
+ 126. test.........................................|SpaceVim-layers-test|
+ 127. tmux.........................................|SpaceVim-layers-tmux|
+ 128. tools#dash.............................|SpaceVim-layers-tools-dash|
+ 129. tools#mpv...............................|SpaceVim-layers-tools-mpv|
+ 130. tools#zeal.............................|SpaceVim-layers-tools-zeal|
+ 131. treesitter.............................|SpaceVim-layers-treesitter|
+ 132. ui.............................................|SpaceVim-layers-ui|
+ 133. unite.......................................|SpaceVim-layers-unite|
7. Usage....................................................|SpaceVim-usage|
1. alternate file........................|SpaceVim-usage-alternate-file|
2. buffers-and-files..................|SpaceVim-usage-buffers-and-files|
@@ -4957,6 +4958,16 @@ KEY BINDINGS
<
+==============================================================================
+LANG#VERILOG *SpaceVim-layers-lang-verilog*
+
+This layer is for verilog development, disabled by default, to enable this
+layer, add following snippet to your SpaceVim configuration file.
+>
+ [[layers]]
+ name = 'lang#verilog'
+<
+
==============================================================================
LANG#VIM *SpaceVim-layers-lang-vim*
diff --git a/docs/cn/layers/lang/verilog.md b/docs/cn/layers/lang/verilog.md
new file mode 100644
index 000000000..bc57f58c6
--- /dev/null
+++ b/docs/cn/layers/lang/verilog.md
@@ -0,0 +1,28 @@
+---
+title: "SpaceVim lang#verilog 模块"
+description: "这一模块为 verilog 开发提供支持，包括交互式编程、一键运行等特性。"
+lang: zh
+---
+
+# [可用模块](../../) >> lang#verilog
+
+
+
+- [模块简介](#模块简介)
+- [启用模块](#启用模块)
+
+
+
+## 模块简介
+
+这一模块为在 SpaceVim 中进行 verilog 开发提供了支持。
+
+## 启用模块
+
+可通过在配置文件内加入如下配置来启用该模块：
+
+```toml
+[[layers]]
+ name = "lang#verilog"
+```
+
diff --git a/docs/layers/lang/verilog.md b/docs/layers/lang/verilog.md
new file mode 100644
index 000000000..625e41cc4
--- /dev/null
+++ b/docs/layers/lang/verilog.md
@@ -0,0 +1,27 @@
+---
+title: "SpaceVim lang#verilog layer"
+description: "This layer is for verilog development, provides syntax checking, code runner and repl support for verilog files."
+---
+
+# [Available Layers](../../) >> lang#verilog
+
+
+
+- [Description](#description)
+- [Install](#install)
+
+
+
+## Description
+
+This layer is for verilog development.
+
+## Install
+
+To use this configuration layer, update your custom configuration file with:
+
+```toml
+[[layers]]
+ name = "lang#verilog"
+```
+