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766 lines
26 KiB
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766 lines
26 KiB
Plaintext
*verilog_systemverilog.txt* Verilog/SystemVerilog Syntax
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Author: Vitor Antunes <vitor.hda@gmail.com>
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Licence: Vim licence, see |license|
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Homepage: http://vhda.github.com/verilog_systemverilog.vim/
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Version: 3.0
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==============================================================================
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Contents *verilog_systemverilog* *verilog-contents*
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1. About .................................... |verilog-about|
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2. Requirements ............................. |verilog-requirements|
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3. Installation ............................. |verilog-installation|
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4. Usage .................................... |verilog-usage|
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Omni-completion ........................ |verilog-omni|
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Syntax folding ......................... |verilog-fold|
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Verilog error formats .................. |verilog-efm|
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Verilog navigation ..................... |verilog-navigate|
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Commands ............................... |verilog-commands|
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Key mappings ........................... |verilog-keys|
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5. Configuration ............................ |verilog-config|
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Indent configuration ................... |verilog-config-indent|
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Syntax configuration ................... |verilog-config-syntax|
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General configuration .................. |verilog-config-general|
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6. Frequently Asked Questions ............... |verilog-faq|
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7. History .................................. |verilog-history|
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8. Credits .................................. |verilog-credits|
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==============================================================================
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1. About *verilog-about*
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Besides some bug corrections, the following features were added to this set of
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scripts:
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- Omni completion.
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- Configurable syntax folding.
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- Context based indentation.
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- Matchit settings to support Verilog 2001 and SystemVerilog.
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- Error format definitions for common Verilog tools.
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- Commands for code navigation.
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==============================================================================
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2. Requirements *verilog-requirements*
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The following requirements have to be met in order to be able to use tagbar:
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- Exuberant ctags 5.5 or higher. Ctags is the program that generates the
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tag information that Tagbar uses. It is shipped with most Linux
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distributions, otherwise it can be downloaded from the following
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website:
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http://ctags.sourceforge.net/
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The user is responsible for the generation of the |tags| file.
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- Universal ctags is recommended, in particular for SystemVerilog
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environments. Most of the omni completion features require this fork of
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Exuberant ctags. This program is available at:
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https://ctags.io/
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https://github.com/universal-ctags/ctags
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- File type detection must be turned on in vim. This can be done with the
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following command in your |vimrc|:
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>
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filetype on
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<
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See |filetype| for more information.
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- Some functionalities will not work in |restricted-mode| or with
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'compatible' set.
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==============================================================================
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3. Installation *verilog-installation*
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------------------------------------------------------------------------------
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vim-plug
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1. Add the following to your |vimrc|:
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>
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Plug 'vhda/verilog_systemverilog.vim'
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<
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2. Run:
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>
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$ vim +PlugInstall +qall
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<
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------------------------------------------------------------------------------
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Vundle
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1. Add the following to your `vimrc`:
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>
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Plugin 'vhda/verilog_systemverilog.vim'
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<
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2. Run:
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>
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$ vim +PluginInstall +qall
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<
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------------------------------------------------------------------------------
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Pathogen
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>
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$ cd ~/.vim/bundle
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$ git clone https://github.com/vhda/verilog_systemverilog.vim
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<
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==============================================================================
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4. Usage *verilog-usage*
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After installation every Verilog file should automatically be detected as
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`verilog_systemverilog` filetype. Use the following command after opening a
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Verilog or SystemVerilog file to confirm that its |filetype| is properly
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defined:
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>
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:set filetype?
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<
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------------------------------------------------------------------------------
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OMNI COMPLETION *verilog-omni*
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This plugin implements an omni completion function that will offer completion
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suggestions depending on the current context. This will only work if a `.`
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character is found in the keyword behind the cursor. At the moment the
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following contexts are supported:
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1. Module instantiation port names.
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2. Function/task arguments.
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3. Object methods and attributes.
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In order to use omni completion a tags file must be generated using the
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following arguments:
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* `--extra=+q` - Enable hierarchy qualified tags extraction.
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* `--fields=+i` - Enable class inheritance extraction.
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* `-n` - (Optional) Use line number instead of Ex: patterns to identify
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declaration (generates smaller tags file).
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No alternative to Universal ctags was tested, but any tag generation software
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should work seemingly as long as it is able to generate a standard class
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qualified tags file.
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For more information on using omni completion please see help page of
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|`i_CTRL-X_CTRL-O| (the required option |'omnifunc'| is automatically defined
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for the supported file extensions).
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Note: Proper SystemVerilog tag generation requires development version of
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Universal ctags.
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------------------------------------------------------------------------------
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SYNTAX FOLDING *verilog-fold*
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To enable syntax folding set the following option:
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>
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set foldmethod=syntax
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<
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Take into account that all folding is disabled by default and the list of
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items to be folded must be configured using |g:verilog_syntax_fold_lst|.
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------------------------------------------------------------------------------
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VERILOG ERROR FORMATS *verilog-efm*
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This plugin includes the |:compiler| definitions for the following Verilog
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tools:
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* Synopsys VCS (`vcs`)
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* Mentor Modelsim (`msim`)
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* Icarus Verilog (`iverilog`)
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* GPL Cver (`cver`)
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* Synopsys Leda (`leda`)
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* Verilator (`verilator`)
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* NCVerilog (`ncverilog`)
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* SpyGlass (`spyglass`)
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The |:compiler| or |:compiler|! commands can be used to enable these
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definitions on the current buffer or all buffers, respectively.
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Example for `iverilog`:
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>
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:compiler! iverilog
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<
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The command |:VerilogErrorFormat| allows the interactive selection of these
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configurations. In some cases it is also possible to ignore lint and/or
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warning level messages.
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A specific tool can be directly selected calling this command with some
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arguments. Below is an example for `VCS`:
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>
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:VerilogErrorFormat vcs 2
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In this example the second argument disables the detection of lint messages.
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This argument can take the following values:
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1. All messages are detected.
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2. Ignore lint messages.
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3. Ignore lint and warning messages.
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Note: The |:compiler| definitions only configure the |'errorformat'|
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option, so it is always necessary to also setup |'makeprg'| before running
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|:make| to execute the selected tool.
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After doing this Vim will be able to detect error messages displayed by the
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selected tool. Vim will also automatically open the files with errors and
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place the cursor on the error position. To navigate the error list use the
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commands |:cnext| and |:cprevious|.
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For more information check the help page for the |quickfix| vim feature.
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------------------------------------------------------------------------------
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VERILOG NAVIGATION *verilog-navigate*
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Following an Instance~
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A framework is provided to follow a module instance to its module declaration
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as long as its respective entry exists in the tags file. To do so simply
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execute |:VerilogFollowInstance| within the instance to follow it to its
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declaration.
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Alternatively, if the cursor is placed over a port of the instance the command
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|:VerilogFollowPort| can be used to navigate to the module declaration and
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immediately searching for that port.
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The navigation is implemented using tags, so normal |'tagstack'| related
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commands can be used to return from the module declaration. Alternatively, the
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command |:VerilogReturnInstance| can be used for this purpose.
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When |g:verilog_navigate_split| is defined these commands will use Vim window
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splits instead of navigating in the same window.
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These commands can be mapped as following:
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>
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nnoremap <leader>i :VerilogFollowInstance<CR>
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nnoremap <leader>o :VerilogReturnInstance<CR>
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nnoremap <leader>I :VerilogFollowPort<CR>
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<
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Jump to start of current instance~
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The command |:VerilogGotoInstanceStart| is provided to move the cursor to the
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start of the first module instantiation that precedes the current cursor
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location.
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This command can be mapped as following:
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>
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nnoremap <leader>u :VerilogGotoInstanceStart<CR>
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<
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------------------------------------------------------------------------------
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COMMANDS *verilog-commands*
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:VerilogGotoInstanceStart *:VerilogGotoInstanceStart*
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Move cursor to start of instance.
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Cursor position moves to the start of instance declaration if called when
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the cursor is within an instance declaration.
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:VerilogFollowInstance *:VerilogFollowInstance*
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Jump to module declaration of current instance.
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The instance is searched for starting from the current cursor position.
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After that, the module is searched for in the |tags| file and, if found,
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jumps to its defintion using |:tag|.
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:VerilogReturnInstance *:VerilogReturnInstance*
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Jump from module declaration back to previously followed instance.
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Uses |'tagstack'| through |pop| function to return from previously
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followed instance.
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:VerilogFollowPort *:VerilogFollowPort*
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Jump to module declaration of current port and search for it.
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Works as |:VerilogFollowInstance| but searches for keyword under cursor
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after jumping to the module definition.
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:VerilogErrorFormat [{tool} [{level}]] *:VerilogErrorFormat*
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Configure |'errorformat'| for the selected tool.
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If called without arguments it will interactively ask for the tool name
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and, if the tool supports it, the level of error messages to identify in
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the log. This commands then configures |g:verilog_efm_level| accordingly
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and executes |:compiler|! with the selected tool.
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Values supported for {tool}:
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vcs - Synopsys VCS
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msim - Mentor Modelsim
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iverilog - Icarus Verilog
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cver - GPL Cver
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leda - Synopsys Leda
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verilator - Verilator
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ncverilog - Cadence NCVerilog
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spyglass - Synopsys SpyGlass
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Values supported for {level}:
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1 - Mark all messages
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2 - Ignore lint messages
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3 - Ignore lint and warning messages
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Usage example:
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>
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:VerilogErrorFormat vcs 2
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<
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Note: It is necessary to properly setup |'makeprg'| such that the
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configured tool is executed with |:make|. For more information check the
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|quickfix| help page.
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:VerilogFoldingAdd *:VerilogFoldingAdd*
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:VerilogFoldingRemove *:VerilogFoldingRemove*
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Commands with auto-completion to simplify maintenance of
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|g:verilog_syntax_fold_lst|.
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If |c_CTRL-D| is used after these commands a list of valid values is
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suggested. When adding new values only valid and not already enabled
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options are suggested. When removing values only currently enabled values
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are suggested.
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:VerilogDisableIndentAdd *:VerilogDisableIndentAdd*
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:VerilogDisableIndentRemove *:VerilogDisableIndentRemove*
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Commands with auto-completion to simplify maintenance of
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|g:verilog_disable_indent|.
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If |c_CTRL-D| is used after these commands a list of valid values is
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suggested. When adding new values only valid and not already enabled
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options are suggested. When removing values only currently enabled values
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are suggested.
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------------------------------------------------------------------------------
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KEY MAPPINGS *verilog-keys*
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Key mappings are not defined automatically, but it is suggested that the
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following mappings are added to your |vimrc|.
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>
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nnoremap <leader>u :VerilogGotoInstanceStart<CR>
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nnoremap <leader>i :VerilogFollowInstance<CR>
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nnoremap <leader>o :VerilogReturnInstance<CR>
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nnoremap <leader>I :VerilogFollowPort<CR>
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<
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==============================================================================
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5. Configuration *verilog-config*
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------------------------------------------------------------------------------
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INDENT CONFIGURATION *verilog-config-indent*
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*b:verilog_indent_width* *g:verilog_indent_width*
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b:verilog_indent_width~
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g:verilog_indent_width~
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Default: undefined
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Override normal |'shiftwidth'|.
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Example:
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>
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let b:verilog_indent_width = 8
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<
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*b:verilog_indent_assign_fix* *g:verilog_indent_assign_fix*
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b:verilog_indent_assign_fix~
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g:verilog_indent_assign_fix~
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Default: undefined
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Always indent lines following an assignment by a fixed amount.
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By default, the indentation script tries to be smart and aligns the lines
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following the assignment with the start of assigned value, if existing:
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>
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assign y =
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a && b;
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assign z = c &&
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d;
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<
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This behavior is disabled when this option is enabled:
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>
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assign y =
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a && b;
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assign z = c &&
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d;
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<
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Example:
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>
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let b:verilog_indent_assign_fix = 1
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<
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*b:verilog_disable_indent_lst* *g:verilog_disable_indent_lst*
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b:verilog_disable_indent_lst~
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g:verilog_disable_indent_lst~
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Default: "eos"
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Disables indent for specific Verilog/SystemVerilog contexts.
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The following contexts are supported:
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- `module`
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- `interface`
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- `class`
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- `package`
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- `covergroup`
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- `program`
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- `generate`
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- `sequence`
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- `property`
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- `method`
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- `preproc`
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- `conditional`
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- `eos`
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Example:
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>
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let g:verilog_disable_indent_lst = "module,class,interface"
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<
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Disabling indentation of `conditional` will change the following:
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>
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// Default indent
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assign a = cond ? b :
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c ;
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// Disabling 'conditional'
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assign a = cond ? b :
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c ;
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<
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Disabling indentation of `eos` will affect how the closing parentheses of
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modules, functions, tasks, etc. are indented.
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By default:
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>
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module mod(
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input wire a,
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input wire b,
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);
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<
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When disabled:
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>
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module mod(
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input wire a,
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input wire b,
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);
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<
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Note: The commands |:VerilogIndentAdd| and |:VerilogIndentRemove| are
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provided to allow an easier management of this variable.
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------------------------------------------------------------------------------
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SYNTAX CONFIGURATION *verilog-config-syntax*
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*b:verilog_syntax_fold_lst* *g:verilog_syntax_fold_lst*
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b:verilog_syntax_fold_lst~
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g:verilog_syntax_fold_lst~
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Default: undefined
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Enables syntax folding according to the configured values.
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This configuration is a comma-separated string of one or more of the
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following:
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- `class`
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- `function`
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- `task`
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- `specify`
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- `interface`
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- `clocking`
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- `covergroup`
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- `sequence`
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- `property`
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- `block` (`begin`, `end`)
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- `block_nested` (like "block", but allows nesting)
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- `block_named` (like "block", but allows nesting and only folds if `begin` is labelled)
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- `comment` (`/*..*/`)
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- `define` (preprocessor conditional statement)
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- `instance`
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- `all` (enables all above options)
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Set to an empty string to disable syntax folding.
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Example:
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>
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let g:verilog_syntax_fold_lst = "function,task"
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<
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Note: The commands |:VerilogFoldingAdd| and |:VerilogFoldingRemove| are
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provided to allow an easier management of this variable.
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*b:verilog_syntax_custom* *g:verilog_syntax_custom*
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b:verilog_syntax_custom~
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g:verilog_syntax_custom~
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Default: undefined
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Dictionary containing custom syntax declarations.
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Each dictionary key is a list of syntax definitions that is a dictionary
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with the following keys:
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- `keyword` - Space separated list of keywords for a |:syn-keyword| entry.
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- `match` - Match expression for a |:syn-match| entry.
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- `match_start` - Match start expression for a |:syn-region| entry.
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- `match_end` - Match end expression for a |:syn-region| entry.
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- `cluster` - Value to be used in "contains=" in a |:syn-cluster| entry.
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- `highlight` - Highlight to be used on as |:syn-matchgroup|.
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- `syn_argument` - Other optional |:syn-arguments|.
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Examples:
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>
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" Fold on SpyGlass pragmas
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let g:verilog_syntax_custom = {
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\ 'spyglass' : [{
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\ 'match_start' : '\/\/\s*spyglass\s\+disable_block\s\+\z(\(\w\|-\)\+\(\s\+\(\w\|-\)\+\)*\)',
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\ 'match_end' : '\/\/\s*spyglass\s\+enable_block\s\+\z1',
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\ 'syn_argument': 'transparent keepend',
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\ }],
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\ }
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" Fold on consecutive line comments
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let g:verilog_syntax_custom = {
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\ 'comment' : [{
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\ 'match_start' : '^\s*//',
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\ 'match_end' : '^\%(\s*//\)\@!',
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\ 'syn_argument': 'contains=verilogTodo,verilogDirective,@Spell keepend extend'
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\ }],
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\ }
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<
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*g:verilog_disable_constant_highlight*
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g:verilog_disable_constant_highlight~
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Default: undefined
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Disables constants highlight.
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This is useful when coding guidelines require keywords starting in
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uppercase that are not constants.
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*g:verilog_quick_syntax*
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g:verilog_quick_syntax~
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Default: undefined
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When enabled, syntax regions will not be defined with Vim's 'syntax'
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command. This can help performance if you are using an old machine or
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viewing a large file such as a netlist. This can be useful if you don't
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care about automatic indentation but still wish to have syntax coloring.
|
|
|
|
WARNING: Enabling this will change the behaviour of indentation as the
|
|
indentation script uses the syntax regions to determine the nested
|
|
context.
|
|
|
|
------------------------------------------------------------------------------
|
|
ERROR FORMAT CONFIGURATION *verilog-config-efm*
|
|
|
|
*g:verilog_efm_level*
|
|
g:verilog_efm_level~
|
|
Default: undefined
|
|
|
|
Determines which types of messages are added to |'errorformat'| for
|
|
detection. When undefined, all messages are detected. The following values
|
|
are supported:
|
|
- `error` - Only Error level messages are detected.
|
|
- `warning` - Error and Warning level messages are detected.
|
|
- `lint` - All messages are detected.
|
|
|
|
Example:
|
|
|
|
>
|
|
let g:verilog_efm_level = "error"
|
|
<
|
|
|
|
*g:verilog_efm_uvm_lst*
|
|
g:verilog_efm_uvm_lst~
|
|
Default: undefined
|
|
|
|
When enabled, appends UVM message formats to |'errorformat'|.
|
|
This configuration is a comma-separated string of one or more of the
|
|
following:
|
|
- `fatal`
|
|
- `error`
|
|
- `warning`
|
|
- `info`
|
|
- `all` (enables all above options)
|
|
|
|
Example:
|
|
|
|
>
|
|
let g:verilog_efm_uvm_lst = "all"
|
|
let g:verilog_efm_uvm_lst = "fatal,error,warning"
|
|
<
|
|
|
|
Note: The commands |:VerilogErrorUVMAdd| and |:VerilogErrorUVMRemove| are
|
|
provided to allow an easier management of this variable.
|
|
|
|
*g:verilog_efm_quickfix_clean*
|
|
g:verilog_efm_quickfix_clean~
|
|
Default: undefined
|
|
|
|
When enabled, appends global matching string to |'errorformat'| such that
|
|
any message that does not match any preceding rule will not appear in the
|
|
|quickfix| window. This will result in a clean quickfix window, where only
|
|
parsed messages are shown.
|
|
|
|
Example:
|
|
|
|
>
|
|
let g:verilog_efm_quickfix_clean = 1
|
|
<
|
|
|
|
*g:verilog_efm_custom*
|
|
g:verilog_efm_custom~
|
|
Default: undefined
|
|
|
|
Allows appending custom |'errorformat'| rules.
|
|
|
|
Example:
|
|
|
|
>
|
|
let g:verilog_efm_custom = %t:\ %m
|
|
<
|
|
|
|
------------------------------------------------------------------------------
|
|
NAVIGATION CONFIGURATION *verilog-config-navigation*
|
|
|
|
*g:verilog_navigate_split*
|
|
g:verilog_navigate_split~
|
|
Default: undefined
|
|
|
|
Opens a split when following an instance.
|
|
Makes use of |:wincmd| and supports the same arguments. In particular:
|
|
- undefined - Split not opened when following instances
|
|
- `"s"` - Opens horizontal split
|
|
- `"v"` - Opens vertical split
|
|
|
|
Example:
|
|
|
|
>
|
|
let g:verilog_navigate_split = 1
|
|
<
|
|
|
|
*g:verilog_navigate_split_close*
|
|
g:verilog_navigate_split_close~
|
|
Default: undefined
|
|
|
|
Command to execute when returning from an instance, when split is enabled.
|
|
The command |:quit| is used by default when this variable is undefined.
|
|
|
|
Example:
|
|
|
|
>
|
|
let g:verilog_navigate_split_close = "bdel"
|
|
<
|
|
|
|
------------------------------------------------------------------------------
|
|
GENERAL CONFIGURATION *verilog-config-general*
|
|
|
|
*b:verilog_verbose* *g:verilog_verbose*
|
|
b:verilog_verbose~
|
|
g:verilog_verbose~
|
|
Default: undefined
|
|
|
|
Enable verbose messaging of the various components of this plugin.
|
|
Messages can be reviewed using |:messages|.
|
|
|
|
Example:
|
|
|
|
>
|
|
let g:verilog_verbose = 1
|
|
<
|
|
|
|
==============================================================================
|
|
6. Frequently Asked Questions *verilog-faq*
|
|
|
|
------------------------------------------------------------------------------
|
|
How to configure certain features only on some files?
|
|
|
|
Many configurations support both buffer local and global variables, allowing
|
|
using default configurations together with local expections. This provides the
|
|
simplicity of using global variables that do not require |:autocmd| for users
|
|
that do not require exceptions, together with the versatily of buffer local
|
|
variables for those that need it.
|
|
|
|
The following example allows using different settings for Verilog and
|
|
SystemVerilog files:
|
|
|
|
>
|
|
let g:verilog_indent_width=2
|
|
augroup verilog_indent_width
|
|
autocmd!
|
|
autocmd BufNewFile,BufRead *.sv let b:verilog_indent_width=4
|
|
augroup END
|
|
<
|
|
Another example that uses a different configuration for files inside a
|
|
specific folder:
|
|
>
|
|
let g:verilog_indent_width=2
|
|
augroup verilog_indent_width
|
|
autocmd!
|
|
autocmd BufNewFile,BufRead */test/*.sv let b:verilog_indent_width=4
|
|
augroup END
|
|
<
|
|
For more information regarding supported patterns check |autocmd-patterns|.
|
|
|
|
------------------------------------------------------------------------------
|
|
Why is opening Verilog/SystemVerilog files so slow?
|
|
|
|
If you are working with files which are over thousands of lines in length,
|
|
then having folding enabled can significantly slow down opening these files. A
|
|
workaround is to add the following to your |.vimrc| (adjust variables as you
|
|
see fit):
|
|
>
|
|
augroup systemverilog_settings_2
|
|
au!
|
|
" Enable folding for normal size files. Folding is really slow for large files.
|
|
au Filetype verilog_systemverilog if line('$') < 2000
|
|
au Filetype verilog_systemverilog let g:verilog_syntax_fold_lst = "all"
|
|
au Filetype verilog_systemverilog syntax enable "Trigger fold calculation
|
|
au Filetype verilog_systemverilog else
|
|
au Filetype verilog_systemverilog let g:verilog_syntax_fold_lst = ""
|
|
au Filetype verilog_systemverilog endif
|
|
augroup END
|
|
<
|
|
|
|
==============================================================================
|
|
7. History *verilog-history*
|
|
|
|
3.0 (2016-05-17)
|
|
- Reimplementation of indentation script (Lewis Russell)
|
|
- Various improvements to omni-completion scripts
|
|
- Add function to control errorformat configuration
|
|
- Add first functions for code navigation
|
|
- Replace assertion with generic label highlight
|
|
- Big revamp of syntax folding
|
|
- Add automatic testing for folding and indentation
|
|
- Add Travis support for automatic regression checking
|
|
- Add vim help
|
|
|
|
2.0 (2015-01-07)
|
|
- Add matchit configuration
|
|
- Implement initial omni-completion
|
|
- Add syntax folding support
|
|
- Highlight to objects and methods
|
|
- Small updates to indentation script
|
|
- Add first test files
|
|
|
|
1.2 (2010-10-18)
|
|
- Added new highlight group for SVA Assertions
|
|
- Fixed conflicting function names in indentation script
|
|
|
|
1.1 (2006-06-28)
|
|
- Added indentation script
|
|
|
|
1.0 (2006-06-26)
|
|
- Initial release
|
|
|
|
==============================================================================
|
|
8. Credits *verilog-credits*
|
|
|
|
The plugin verilog_systemverilog was originally created by Amit Sethi, with
|
|
the original indent script created by Chih-Tsun Huang. The original plugin is
|
|
available at the following location:
|
|
|
|
http://www.vim.org/scripts/script.php?script_id=1586
|
|
|
|
No license was included with the original files, as such it was assumed it was
|
|
released under the Vim |license|.
|
|
|
|
This plugin is maintained by Vitor Antunes and released under the Vim
|
|
|license|.
|
|
|
|
Thanks to the following people for code contributions, feature suggestions, etc:
|
|
Lewis Russell
|
|
Greg Hilton
|
|
decrement
|
|
Kit Monisit
|
|
Leo Butlero
|
|
|
|
==============================================================================
|
|
vim: tw=78 ts=8 sw=4 sts=4 et ft=help
|