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394 lines
3.9 KiB
Systemverilog
Vendored
394 lines
3.9 KiB
Systemverilog
Vendored
module #(
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parameter TEST1 = $clog(0),
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parameter TEST2 = $clog(1),
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parameter TEST3 = $clog(2)
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) mymodule(
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input wire a,
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input wire b,
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`ifdef MACRO
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input wire c,
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`endif
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output wire y
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);
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othermodule #(.something (a),
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.somethingelse(b)
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) inst(.p1(), .p2(), .p3 (),
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.p4(),
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.p5(), .p6(), .p7(),
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.p8 ()
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.p9 (a)
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);
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mymod MOD(.IN1(), .IN2(), .OP(),
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.OUT());
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endmodule
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`define DEF_WITH_EQ = 1'b0
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`define DEF_MULTI_LINE cond(a,b,c) \
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a ? b : c
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`ifdef SYSTEM_VERILOG_KEYWORDS
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accept_on
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alias
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always
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always_comb
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always_ff
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always_latch
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and
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assert
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assign
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assume
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automatic
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before
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begin
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end
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bind
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bins
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binsof
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bit
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break
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buf
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bufif0
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bufif1
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byte
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case
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casex
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casez
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cell
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chandle
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checker
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cmos
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config
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const
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constraint
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context
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continue
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cover
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coverpoint
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cross
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deassign
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default
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defparam
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design
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disable
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dist
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do
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edge
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else
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endcase
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endchecker
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endconfig
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endgenerate
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endpackage
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endprimitive
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endprogram
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endtable
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enum
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event
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eventually
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expect
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export "DPI-SC" task exported_task;
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extends
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extern
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final
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first_match
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for
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force
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foreach
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forever
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fork
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forkjoin
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generate
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genvar
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global
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highz0
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highz1
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if
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iff
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ifnone
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ignore_bins
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illegal_bins
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implements
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implies
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import
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incdir
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include
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initial
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inout
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input
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inside
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instance
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int
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integer
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interconnect
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intersect
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join
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join_any
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join_none
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large
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let
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liblist
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library
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local
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localparam
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logic
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longint
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macromodule
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mailbox
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matches
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medium
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modport
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nand
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negedge
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nettype
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new
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nexttime
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nmos
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nor
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noshowcancelled
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not
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notif0
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notif1
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null
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or
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output
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package
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packed
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parameter
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pmos
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posedge
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primitive
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priority
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program
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protected
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pull0
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pull1
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pulldown
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pullup
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pulsestyle_ondetect
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pulsestyle_onevent
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pure
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rand
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randc
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randcase
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randsequence
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rcmos
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real
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realtime
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ref
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reg
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reject_on
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release
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repeat
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restrict
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return
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rnmos
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rpmos
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rtran
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rtranif0
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rtranif1
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s_always
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s_eventually
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s_nexttime
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s_until
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s_until_with
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scalared
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semaphore
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shortint
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shortreal
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showcancelled
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signed
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small
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soft
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solve
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specparam
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static
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string
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strong
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strong0
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strong1
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struct
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super
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supply0
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supply1
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sync_accept_on
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sync_reject_on
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table
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tagged
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this
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throughout
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time
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timeprecision
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timeunit
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tran
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tranif0
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tranif1
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tri
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tri0
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tri1
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triand
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trior
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trireg
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type
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union
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unique
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unique0
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unsigned
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until
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until_with
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untyped
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use
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uwire
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var
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vectored
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virtual
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void
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wait
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wait_order
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wand
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weak
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weak0
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weak1
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while
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wildcard
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wire
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with
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within
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wor
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xnor
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xor
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// Syntax regions
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typedef;
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class
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endclass
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clocking
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endclocking
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covergroup
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endgroup
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function
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endfunction
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interface
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endinterface
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module
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endmodule
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property
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endproperty
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sequence
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endsequence
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specify
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endspecify
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task
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endtask
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`endif
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`ifdef COMPLEX_STATEMENTS
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typedef class c;
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`endif
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`ifdef TIME
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10ns
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100ns
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1ps
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2_0ps
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3_000_000s
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1.23ns
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1_000.123ns
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10_000.123ns
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100_000.123ns
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1_000_000.123ns
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1.2.3ns // Second to should not be part of number syntax
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1step
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`endif
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`ifdef NUMBERS
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4'h0
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4'h1
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4'h2
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4'h3
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4'h4
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4'h5
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4'h6
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4'h7
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4'h8
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4'h9
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4'ha
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4'hb
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4'hc
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4'hd
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4'he
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4'hf
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4'hA
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4'hB
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4'hC
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4'hD
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4'hE
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4'hF
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4'hg // Invalid value for hexadecimal number
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4'hG // Invalid value for hexadecimal number
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3'o0
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3'o1
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3'o2
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3'o3
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3'o4
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3'o5
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3'o6
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3'o7
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3'o8 // Invalid value for octal number
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3'b0_01
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3'b001
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3'b_01
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3'b120 // Invalid value for binary number
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'd10000
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'd_000_000
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'd_x00_000
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4'b0?x0
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4'b010?
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4'b010? ? 4'b????; // Conditional '?' and ';' should not be part of number syntax
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`endif
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// synopsys
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/* synopsys dc_script_begin
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* set_size_only {U1}
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* synopsys dc_script_end
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*/
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// synopsys dc_script_begin
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// set_size_only {U1}
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// synopsys dc_script_end
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// TODO todo check
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/*
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* TODO todo check
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*/
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/*//my comment */
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//my /*comment*/
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// Code from: https://github.com/vhda/verilog_systemverilog.vim/issues/186
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string foo = "bar, baz";
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int foo2 = 0;
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// End of copied code
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// Comment with DEFINE-ML
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always@(posedge clk or posedge rst)
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begin
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priority if (rst)
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state <= IDLE;
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else
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state <= NS;
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end
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always @(*) begin : label
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if (a) begin
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y = c, z = a;
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end else begin
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y = d, z = b;
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end
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end
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assign a = myfunc(this);
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// vi: set expandtab softtabstop=4 shiftwidth=4:
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